scholarly journals Adaptive Abstraction-Level Conversion Framework for Accelerated Discrete-Event Simulation in Smart Semiconductor Manufacturing

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 165247-165262
Author(s):  
Moon Gi Seok ◽  
Wentong Cai ◽  
Hessam S. Sarjoughian ◽  
Daejin Park
2014 ◽  
pp. 158-169
Author(s):  
Bakhta Meroufel ◽  
Ghalem Belalem

A common approach to guarantee an acceptable level of fault tolerance in scientific computing is the checkpointing. In this strategy: when a task fails, it is allowed to be restarted from the recently checked pointed state rather than from the beginning, which reduces the system loss and ensures the reliability. Several systems use the checkpointing to ensure the fault tolerance such as HPC, distributed discrete event simulation and Clouds. The literature proposes several classifications of checkpointing techniques using different metrics and criteria. In this paper we focus on the classification based on abstraction level. In this classification the checkpointing is categorized into two principal types: application level and system level. Each of these levels has its advantages and suffers from many problems. The difference between our present paper and the others surveys proposed in the literature is that: in this paper we will study each level in details. We will also study and analyze some works that propose solutions to solve the problems and exceed the limits of each abstraction level.


Author(s):  
Markus Pfeffer ◽  
Richard Oechsner ◽  
Lothar Pfitzner ◽  
Heiner Ryssel ◽  
Berthold Ocker ◽  
...  

Semiconductor wafer fabrication facilities (wafer fabs) are amongst the most complex production facilities. State-of-the-art wafer fabs comprise a large product variety, hundreds of processing steps per product, almost hundreds of machines of different types, and automated transportation systems combined with reentrant flows throughout the fab. In addition to the high complexity, wafer fabs require very high capital investment and an undisturbed operation. Semiconductor manufacturers are facing fierce competition as more global capacity is being added. Through this intense competition, semiconductor manufacturers have to improve their processes from a technological as well as from a logistical point of view in order to be successful within the global market. The logistics not only involves fab wide optimization strategies but also the individual equipment performance, for example cycle time and throughput, has to be considered. In this paper, the need for performance optimization of semiconductor manufacturing equipment is identified and the capability of discrete event simulation for such optimizations is being elaborated. Characteristics of different types of simulation models are described and the simulation model selection is explained. For case studies, several simulation models of different semiconductor manufacturing equipment have been developed. Using five examples, different optimization strategies, dependent on the application of the semiconductor manufacturing equipment, have been investigated by discrete event simulation. The paper shows the influence of the integration of metrology into deposition equipment, the impact of different batch sizes for oxidation processes, and the optimized dimensioning of photolithography equipment. Furthermore, the throughput and cycle time of different deposition equipment are optimized by the evaluation of various improvement strategies. All investigations have been performed with real data extracted from already utilized equipment or at least with data from the equipment suppliers of prototype equipment.


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