Area Efficient Pipelined VLSI Implementation of List Sphere Decoder

2006 Asia-Pacific Conference on Communications ◽

10.1109/apcc.2006.255901 ◽

2006 ◽

Author(s):

Jin Lee ◽

Sin-chong Park

Keyword(s):

Vlsi Implementation ◽

Sphere Decoder ◽

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VLSI Implementation of Area-efficient List Sphere Decoder

2006 International Conference on Communication Technology ◽

10.1109/icct.2006.341862 ◽

2006 ◽

Author(s):

Seungbeom Lee ◽

Jin Lee ◽

Sin-Chong Park

Keyword(s):

Vlsi Implementation ◽

Sphere Decoder ◽

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VLSI Implementation of Area-efficient List Sphere Decoder

2006 International Symposium on Intelligent Signal Processing and Communications ◽

10.1109/ispacs.2006.364730 ◽

2006 ◽

Author(s):

Seungbeom Lee ◽

Jin Lee ◽

Sang-ho Seo ◽

Sin-Chong Park

Keyword(s):

Vlsi Implementation ◽

Sphere Decoder ◽

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

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An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

Journal of Systems Architecture ◽

10.1016/j.sysarc.2008.05.006 ◽

2008 ◽

Vol 54 (12) ◽

pp. 1122-1128 ◽

Author(s):

Thomas Poonnen ◽

Adly T. Fam

Keyword(s):

Vlsi Implementation ◽

Divide And Conquer ◽

Fir Filters ◽

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VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2013.2251954 ◽

2013 ◽

Vol 60 (5) ◽

pp. 272-276 ◽

Author(s):

Xi Chen ◽

Guanghui He ◽

Jun Ma

Keyword(s):

High Throughput ◽

Vlsi Implementation ◽

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Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2012.2195062 ◽

2012 ◽

Vol 59 (6) ◽

pp. 371-375 ◽

Author(s):

Yu-Chi Tsao ◽

Ken Choi

Keyword(s):

Digital Filters ◽

Vlsi Implementation ◽

Linear Phase ◽

Fir Digital Filters ◽

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VLSI implementation of a quasi-ml, energy efficient fixed complexity sphere decoder for MIMO communication system

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5537824 ◽

2010 ◽

Author(s):

Kelvin Lee ◽

Babak Daneshrad

Keyword(s):

Communication System ◽

Energy Efficient ◽

Vlsi Implementation ◽

Mimo Communication ◽

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VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

Arabian Journal for Science and Engineering ◽

10.1007/s13369-014-1329-7 ◽

2014 ◽

Vol 39 (11) ◽

pp. 7795-7806 ◽

Author(s):

K. N. Vijeyakumar ◽

V. Sumathy ◽

S. Elango

Keyword(s):

Signal Processing ◽

Vlsi Implementation ◽

Booth Multiplier ◽

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An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) ◽

10.1109/icm.2003.238420 ◽

2003 ◽

Author(s):

T. Poonnen ◽

A.T. Fam

Keyword(s):

Vlsi Implementation ◽

Divide And Conquer ◽

Fir Filters ◽

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VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick

2019 International SoC Design Conference (ISOCC) ◽

10.1109/isocc47750.2019.9027759 ◽

2019 ◽

Author(s):

Tae Koan Yoo ◽

Jong Kang Park ◽

Jong Tae Kim

Keyword(s):

Neural Network ◽

Vlsi Implementation ◽

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