VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick

2019 International SoC Design Conference (ISOCC) ◽

10.1109/isocc47750.2019.9027759 ◽

2019 ◽

Author(s):

Tae Koan Yoo ◽

Jong Kang Park ◽

Jong Tae Kim

Keyword(s):

Neural Network ◽

Vlsi Implementation ◽

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

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VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators

Microprocessors and Microsystems ◽

10.1016/j.micpro.2021.104270 ◽

2021 ◽

pp. 104270

Author(s):

Gunjan Rajput ◽

Gopal Raut ◽

Mahesh Chandra ◽

Santosh Kumar Vishvakarma

Keyword(s):

Neural Network ◽

Deep Neural Network ◽

Vlsi Implementation ◽

Transcendental Function ◽

Hyperbolic Tangent

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An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

Journal of Systems Architecture ◽

10.1016/j.sysarc.2008.05.006 ◽

2008 ◽

Vol 54 (12) ◽

pp. 1122-1128 ◽

Author(s):

Thomas Poonnen ◽

Adly T. Fam

Keyword(s):

Vlsi Implementation ◽

Divide And Conquer ◽

Fir Filters ◽

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A coded block neural network system suitable for VLSI implementation using an adaptive learning-rate epoch-based back propagation technique

1993 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1993.394137 ◽

2002 ◽

Author(s):

M.W. Mao ◽

B.Y. Chen ◽

J.B. Kuo

Keyword(s):

Neural Network ◽

Adaptive Learning ◽

Back Propagation ◽

Learning Rate ◽

Vlsi Implementation ◽

Network System ◽

Adaptive Learning Rate ◽

Neural Network System ◽

Propagation Technique

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Area-Efficient Series-Connected Resonant Tunneling Diode Pair as Binary Neuron in Cellular Neural Network

IEEE Electron Device Letters ◽

10.1109/led.2020.3008164 ◽

2020 ◽

Vol 41 (9) ◽

pp. 1308-1311

Author(s):

Jongwon Lee ◽

Sunkyu Choi ◽

Seong-Yeon Kim ◽

Jooseok Lee ◽

Kyounghoon Yang

Keyword(s):

Neural Network ◽

Resonant Tunneling ◽

Cellular Neural Network ◽

Resonant Tunneling Diode ◽

Tunneling Diode ◽

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Area Efficient Pipelined VLSI Implementation of List Sphere Decoder

2006 Asia-Pacific Conference on Communications ◽

10.1109/apcc.2006.255901 ◽

2006 ◽

Author(s):

Jin Lee ◽

Sin-chong Park

Keyword(s):

Vlsi Implementation ◽

Sphere Decoder ◽

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VLSI implementation of a Cellular Neural Network with programmable control operator

Proceedings of 36th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1993.343274 ◽

2002 ◽

Author(s):

G.C. Cardarilli ◽

R. Lojacono ◽

M. Salerno ◽

F. Sargeni

Keyword(s):

Neural Network ◽

Cellular Neural Network ◽

Vlsi Implementation ◽

Control Operator

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VLSI implementation of a fully parallel stochastic neural network

Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94) ◽

10.1109/icnn.1994.374527 ◽

2002 ◽

Author(s):

J.M. Quero ◽

J.G. Ortega ◽

C.L. Janer ◽

L.G. Franquelo

Keyword(s):

Neural Network ◽

Vlsi Implementation ◽

Stochastic Neural Network

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Compact VLSI implementation of cellular neural network

Proceedings of the 39th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1996.594214 ◽

2002 ◽

Author(s):

A. Paasio ◽

A. Dawidziuk ◽

V. Porra

Keyword(s):

Neural Network ◽

Cellular Neural Network ◽

Vlsi Implementation

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VLSI implementation of a neural network classifier

Proceedings of 1996 Canadian Conference on Electrical and Computer Engineering ◽

10.1109/ccece.1996.548066 ◽

2002 ◽

Author(s):

R.L.K. Mandisodza ◽

D.M. Luke ◽

P. Pochec

Keyword(s):

Neural Network ◽

Vlsi Implementation ◽

Neural Network Classifier

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