VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder

2013 ◽  
Vol 60 (5) ◽  
pp. 272-276 ◽  
Author(s):  
Xi Chen ◽  
Guanghui He ◽  
Jun Ma
Keyword(s):  
High Throughput ◽  
Vlsi Implementation ◽  
Sphere Decoder

scholarly journals VLSI IMPLEMENTATION OF WiMax CONVOLUTIONAL TURBO CODE ENCODER AND DECODER

2009 ◽  
Vol 18 (03) ◽  
pp. 535-564 ◽  
Author(s):  
MAURIZIO MARTINA ◽  
MARIO NICOLA ◽  
GUIDO MASERA
Keyword(s):  
High Throughput ◽  
Turbo Code ◽  
Ieee 802.16 ◽  
Vlsi Implementation ◽  
Standard Cell ◽  
Clock Frequency ◽  
Cell Technology

A VLSI encoder and decoder implementation for the IEEE 802.16 WiMax convolutional turbo code is presented. Architectural choices employed to achieve high throughput, while granting a limited occupation of resources, are addressed both for the encoder and decoder side, including also the subblock interleaving and symbol selection functions specified in the standard. The complete encoder and decoder architectures, implemented on a 0.13 μm standard cell technology, sustain a decoded throughput of more than 90 Mb/s with a 200 MHz clock frequency. The encoder has the complexity of 9.2 kgate of logic and 187.2 kbit of memory, whereas the complete decoder requires 167.7 kgate and 1163 kbit.

Sign in / Sign up

Export Citation Format

Share Document