A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture

2013 IEEE 10th International Conference on ASIC ◽

10.1109/asicon.2013.6811834 ◽

2013 ◽

Author(s):

Gui Feng ◽

Fen Ge ◽

Shuang Yu ◽

Ning Wu

Keyword(s):

Network On Chip ◽

Mesh Network ◽

3D Mesh ◽

Mapping Algorithm ◽

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Accurate Performance Analysis of 3D Mesh Network on Chip Architectures

2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) ◽

10.1109/conecct.2018.8482383 ◽

2018 ◽

Author(s):

Bheemappa Halavar ◽

Basavaraj Talawar

Keyword(s):

Performance Analysis ◽

Network On Chip ◽

Mesh Network ◽

3D Mesh ◽

Accurate Performance ◽

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An efficient mapping algorithm on 2-D mesh Network-on-Chip with reconfigurable switches

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis.2016.7483808 ◽

2016 ◽

Author(s):

Salih Bayar ◽

Arda Yurdakul

Keyword(s):

Network On Chip ◽

Mesh Network ◽

Mapping Algorithm ◽

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OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip

2015 28th International Conference on VLSI Design ◽

10.1109/vlsid.2015.23 ◽

2015 ◽

Author(s):

Ramon Fernandes ◽

Lucas Brahm ◽

Thais Webber ◽

Rodrigo Cataldo ◽

Leticia B. Poehls ◽

...

Keyword(s):

Network On Chip ◽

Mesh Network ◽

3D Mesh ◽

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A minimum-path mapping algorithm for 2D mesh Network on Chip architecture

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2008.4746327 ◽

2008 ◽

Author(s):

Ge Fen ◽

Wu Ning

Keyword(s):

Network On Chip ◽

Mesh Network ◽

Mapping Algorithm ◽

Minimum Path ◽

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Scalable Design and Synthesis of 3D Mesh Network on Chip

Proceeding of International Conference on Intelligent Communication, Control and Devices - Advances in Intelligent Systems and Computing ◽

10.1007/978-981-10-1708-7_75 ◽

2016 ◽

pp. 661-666

Author(s):

Arpit Jain ◽

Rakesh Dwivedi ◽

Adesh Kumar ◽

Sanjeev Sharma

Keyword(s):

Network On Chip ◽

Mesh Network ◽

3D Mesh ◽

Design And Synthesis ◽

On Chip ◽

Scalable Design

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Restricted Turn Model Fault Tolerant Routing Techniques for 3D Mesh Network-on-Chip: An Evaluation

Information and Communication Technology - Advances in Intelligent Systems and Computing ◽

10.1007/978-981-10-5508-9_10 ◽

2017 ◽

pp. 113-122

Author(s):

Ravindra Kumar Saini ◽

Mushtaq Ahmed

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Mesh Network ◽

3D Mesh ◽

Routing Techniques ◽

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Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) ◽

10.1109/aspdac.2011.5722213 ◽

2011 ◽

Author(s):

Cheng Liu ◽

Lei Zhang ◽

Yinhe Han ◽

Xiaowei Li

Keyword(s):

Network On Chip ◽

Mesh Network ◽

3D Mesh ◽

Vertical Interconnects ◽

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2D Hexagonal Mesh Vs 3D Mesh Network on Chip: A Performance Evaluation

International Journal of Computing and Digital Systems ◽

10.12785/ijcds/040104 ◽

2015 ◽

Vol 3 (3) ◽

pp. 33-41 ◽

Author(s):

Ravindra Kumar Saini, et. al.

Keyword(s):

Performance Evaluation ◽

Network On Chip ◽

Mesh Network ◽

3D Mesh ◽

On Chip ◽

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A multi-wavelength communication strategy for 2D-mesh Network-on-Chip

IEICE Electronics Express ◽

10.1587/elex.9.706 ◽

2012 ◽

Vol 9 (7) ◽

pp. 706-711

Author(s):

Xiaoshan Yu ◽

Huaxi Gu ◽

Yingtang Yang ◽

Luying Bai ◽

Hua You

Keyword(s):

Network On Chip ◽

Communication Strategy ◽

Mesh Network ◽

Multi Wavelength ◽

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Low-power mapping algorithm for three-dimensional network-on-chip based on diversity-controlled quantum-behaved particle swarm optimization

Journal of Algorithms & Computational Technology ◽

10.1177/1748301816649070 ◽

2016 ◽

Vol 10 (3) ◽

pp. 176-186 ◽

Author(s):

Cui Huang ◽

Dakun Zhang ◽

Guozhi Song

Keyword(s):

Particle Swarm Optimization ◽

Low Power ◽

Three Dimensional ◽

Particle Swarm ◽

Network On Chip ◽

Swarm Optimization ◽

Mapping Algorithm ◽

Dimensional Network ◽

On Chip ◽

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