Restricted Turn Model Fault Tolerant Routing Techniques for 3D Mesh Network-on-Chip: An Evaluation

Author(s):  
Ravindra Kumar Saini ◽  
Mushtaq Ahmed
2017 ◽  
Vol 27 (02) ◽  
pp. 1850022 ◽  
Author(s):  
Ling Wang ◽  
Terrence Mak

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.


Author(s):  
Akshay B. P. ◽  
Ganesh K. M. ◽  
Thippeswamy D. R. ◽  
Vishnu S. Bhat ◽  
Anitha Vijayakumar ◽  
...  

2013 ◽  
Vol 29 (3) ◽  
pp. 415-429 ◽  
Author(s):  
Yusuke Fukushima ◽  
Masaru Fukushi ◽  
Ikuko Eguchi Yairi

2014 ◽  
Vol 24 (02) ◽  
pp. 1540006 ◽  
Author(s):  
M. M. Hafizur Rahman ◽  
Rizal Mohd Nor ◽  
Tengku Mohd Bin Tengku Sembok ◽  
M. A. H. Akhand

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.


Integration ◽  
2020 ◽  
Vol 72 ◽  
pp. 92-110
Author(s):  
Anugrah Jain ◽  
Vijay Laxmi ◽  
Meenakshi Tripathi ◽  
Manoj Singh Gaur ◽  
Rimpy Bishnoi

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