Adaptable VLIW processor: The reconfigurable technology approach

2017 International Conference on Advanced Technologies for Communications (ATC) ◽

10.1109/atc.2017.8167600 ◽

2017 ◽

Author(s):

Cuong Pham-Quoc ◽

Binh Kieu-Do-Nguyen ◽

Anh-Vu Dinh-Duc

Keyword(s):

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Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings. ◽

10.1109/micro.2002.1176244 ◽

2003 ◽

Author(s):

E. Gibert ◽

J. Sanchez ◽

A. Gonzalez

Keyword(s):

Effective Instruction ◽

Instruction Scheduling ◽

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Performance evaluation for a compressed-VLIW processor

Proceedings of the 2002 ACM symposium on Applied computing - SAC '02 ◽

10.1145/508791.508967 ◽

2002 ◽

Author(s):

Sunghyun Jee ◽

Kannappan Palaniappan

Keyword(s):

Performance Evaluation ◽

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Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_11 ◽

2008 ◽

pp. 147-160 ◽

Author(s):

Todd T. Hahn ◽

Eric Stotzer ◽

Dineel Sule ◽

Mike Asal

Keyword(s):

Variable Length ◽

Code Size ◽

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Simple Type-Based Alias Analysis for a VLIW Processor

Communications in Computer and Information Science - Tools and Methods of Program Analysis ◽

10.1007/978-3-319-71734-0_9 ◽

2017 ◽

pp. 102-113

Author(s):

Aleksey Markin ◽

Alexandr Ermolitsky

Keyword(s):

Simple Type ◽

Alias Analysis ◽

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Configurable Fault-Tolerance for a Configurable VLIW Processor

Lecture Notes in Computer Science - Reconfigurable Computing: Architectures, Tools and Applications ◽

10.1007/978-3-642-36812-7_16 ◽

2013 ◽

pp. 167-178 ◽

Author(s):

Fakhar Anjam ◽

Stephan Wong

Keyword(s):

Fault Tolerance ◽

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A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era

IEICE Transactions on Electronics ◽

10.1093/ietele/e88-c.4.552 ◽

2005 ◽

Vol E88-C (4) ◽

pp. 552-558

Author(s):

K. KOBAYASHI

Keyword(s):

Low Power ◽

Vliw Processor ◽

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Exploring Adaptive Cache for Reconfigurable VLIW Processor

IEEE Access ◽

10.1109/access.2019.2919589 ◽

2019 ◽

Vol 7 ◽

pp. 72634-72646

Author(s):

Sensen Hu ◽

Jing Haung

Keyword(s):

Vliw Processor ◽

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Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking

10.1109/asap.2009.11 ◽

2009 ◽

Author(s):

Yangyang Pan ◽

Tong Zhang

Keyword(s):

Three Dimensional ◽

Processor Performance ◽

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A 2 way VLIW processor architecture for embedded multimedia applications

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) ◽

10.1109/sips.1999.822326 ◽

2003 ◽

Author(s):

Jiyang Kang ◽

Jae-Woo Ahn ◽

Jiyoung Cho ◽

Ki-Il Kum ◽

Wonyong Sung

Keyword(s):

Multimedia Applications ◽

Processor Architecture ◽

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Pipelining and bypassing in a VLIW processor

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/71.285612 ◽

1994 ◽

Vol 5 (6) ◽

pp. 658-664 ◽

Author(s):

A. Abnous ◽

N. Bagherzadeh

Keyword(s):

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