Fast prototyping: a system design flow applied to a complex System-On-Chip multiprocessor design

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era

Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era ◽

10.1109/iwv.2000.844519 ◽

2000 ◽

Keyword(s):

System Design ◽

System On Chip ◽

Ieee Computer Society ◽

On Chip

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Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support

Multiprocessor System-on-Chip ◽

10.1007/978-1-4419-6460-1_6 ◽

2010 ◽

pp. 127-151 ◽

Cited By ~ 2

Author(s):

Diana Göhringer ◽

Michael Hübner ◽

Jürgen Becker

Keyword(s):

System Design ◽

Degrees Of Freedom ◽

System On Chip ◽

Multiprocessor System ◽

Runtime Support ◽

On Chip

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Evaluation of GALS Methods in Scaled CMOS Technology

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/jertcs.2012100101 ◽

2012 ◽

Vol 3 (4) ◽

pp. 1-18 ◽

Cited By ~ 2

Author(s):

Miloš Krstic ◽

Xin Fan ◽

Eckhard Grass ◽

Luca Benini ◽

M. R. Kakoee ◽

...

Keyword(s):

Complex System ◽

Cmos Technology ◽

Network On Chip ◽

Design Flow ◽

Cmos Process ◽

Test Results ◽

Experimental Setting ◽

Analysis Measurement ◽

On Chip ◽

Point To Point

In this paper the authors present the concept and evaluation results of a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating its potentials for different applications. The design analysis, measurement and test results confirm the potential of GALS approach for the scaled technologies, showing the significant benefits in respect to area, power, and EMI when it comes to the complex system implementation. Furthermore, 91% of the tests performed on the GALS network-on-chip test structures completed successfully, validating the timing robustness of new area and latency-efficient synchronization schemes and proving that the design flow for GALS synchronization technology can be implemented by means of mainstream industrial tools.

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