A Phase Lead-Lag Synchronous PLL for Grid Synchronization of a Single Phase Inverter

Author(s):  
Jetnarong Pongpaiboon ◽  
Thamvarit Singhvilai ◽  
Supun Tiptipakorn ◽  
Chuttchaval Jeraputra
Author(s):  
Eyad Radwan ◽  
Khalil Salih ◽  
Emad Awada ◽  
Mutasim Nour

Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low order harmonics the estimation of the grid phase angle deteriorates resulting in higher oscillations (errors) appearing in the synchronization voltage signals. This paper proposes a modified time delay PLL (MTDPLL) technique that continuously updates a variable time delay unit to keep track of the variation in the grid frequency. The MTDPLL is implemented along a Multi-Harmonic Decoupling Cell (MHDC) to overcome the effects of distortion caused by gird lower order harmonics. The performance of the proposed MTDPLL is verified by simulation and compared in terms of performance and accuracy with recent PLL techniques.


Sign in / Sign up

Export Citation Format

Share Document