Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

Author(s):  
Aleksei E. Krylov ◽  
Andrey V. Rashich ◽  
Dmitrii K. Fadeev ◽  
Kirill A. Sinjutin
2021 ◽  
Author(s):  
Andrey Rashich ◽  
Aleksei Krylov ◽  
Dmitrii Fadeev ◽  
Kirill Sinjutin

<div>The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.</div>


2021 ◽  
Author(s):  
Andrey Rashich ◽  
Aleksei Krylov ◽  
Dmitrii Fadeev ◽  
Kirill Sinjutin

<div>The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.</div>


2020 ◽  
Vol E103.B (1) ◽  
pp. 43-51 ◽  
Author(s):  
Yuhuan WANG ◽  
Hang YIN ◽  
Zhanxin YANG ◽  
Yansong LV ◽  
Lu SI ◽  
...  

Author(s):  
R. A. Morozov ◽  
P. V. Trifonov

Introduction:Practical implementation of a communication system which employs a family of polar codes requires either to store a number of large specifications or to construct the codes by request. The first approach assumes extensive memory consumption, which is inappropriate for many applications, such as those for mobile devices. The second approach can be numerically unstable and hard to implement in low-end hardware. One of the solutions is specifying a family of codes by a sequence of subchannels sorted by reliability. However, this solution makes it impossible to separately optimize each code from the family.Purpose:Developing a method for compact specifications of polar codes and subcodes.Results:A method is proposed for compact specification of polar codes. It can be considered a trade-off between real-time construction and storing full-size specifications in memory. We propose to store compact specifications of polar codes which contain frozen set differences between the original pre-optimized polar codes and the polar codes constructed for a binary erasure channel with some erasure probability. Full-size specification needed for decoding can be restored from a compact one by a low-complexity hardware-friendly procedure. The proposed method can work with either polar codes or polar subcodes, allowing you to reduce the memory consumption by 15–50 times.Practical relevance:The method allows you to use families of individually optimized polar codes in devices with limited storage capacity. 


2014 ◽  
Author(s):  
David Wasserman
Keyword(s):  

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