scholarly journals Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

2021 ◽  
Author(s):  
Andrey Rashich ◽  
Aleksei Krylov ◽  
Dmitrii Fadeev ◽  
Kirill Sinjutin
Keyword(s):  
Vlsi Architecture ◽  
Priority Queue ◽  
Low Complexity ◽  
Low Latency ◽  
Polar Codes ◽  
Sorting Networks ◽  
Vlsi Architectures ◽  
Simulation Results ◽  
Full Search ◽  
Ber Performance

<div>The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.</div>

scholarly journals Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

2021 ◽  
Author(s):  
Andrey Rashich ◽  
Aleksei Krylov ◽  
Dmitrii Fadeev ◽  
Kirill Sinjutin
Keyword(s):  
Vlsi Architecture ◽  
Priority Queue ◽  
Low Complexity ◽  
Low Latency ◽  
Polar Codes ◽  
Sorting Networks ◽  
Vlsi Architectures ◽  
Simulation Results ◽  
Full Search ◽  
Ber Performance

<div>The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.</div>

A Min-Sum Algorithm Suitable for Hardware Implementation Based on LDPC Codes

2011 ◽  
Vol 271-273 ◽  
pp. 458-463
Author(s):  
Rui Ping Chen ◽  
Zhong Xun Wang ◽  
Xin Qiao Yu
Keyword(s):  
Hardware Implementation ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Scaling Factor ◽  
Computation Complexity ◽  
Decoding Complexity ◽  
Decoding Algorithms ◽  
Hardware Resource ◽  
Simulation Results ◽  
Ber Performance

Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.

Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

2021 ◽  
Author(s):  
Aleksei E. Krylov ◽  
Andrey V. Rashich ◽  
Dmitrii K. Fadeev ◽  
Kirill A. Sinjutin
Keyword(s):  
Vlsi Architecture ◽  
Priority Queue ◽  
Polar Codes

Study of FCLSD Algorithm Performance Based on LTE System

2012 ◽  
Vol 195-196 ◽  
pp. 96-103
Author(s):  
Ke Wen Liu ◽  
Quan Liu
Keyword(s):  
High Performance ◽  
Hardware Implementation ◽  
Low Complexity ◽  
Detection Algorithm ◽  
Sphere Decoding ◽  
Mimo Detection ◽  
Decoding Algorithm ◽  
Algorithm Performance ◽  
Simulation Results ◽  
Ber Performance

Soft-output complex list sphere decoding algorithm is a low-complexity MIMO detection algorithm and its BER performance approximates that of Maximum-Likelihood. However, it has a problem of not fixed complexity, and which make it very difficult to implement. To resolve this and try best to retain the advantages of the algorithm, a modified algorithmfixed complex list sphere decoding algorithm was proposed. Based on LTE TDD system, this paper studies the performance of the FCLSD algorithm. The simulation results show that: the BER performance of the FCLSD algorithm is close to that of the CLSD algorithm. However, when the number of antennas and modulation order increasing, the FCLSD algorithm is non-constrained of spherical radius and has fixed complexity. In addition, hardware implementation of the FCLSD algorithm could be carried out by parallel processing, thereby greatly reducing the algorithm complexity. So it is a high-performance algorithm of great potential.

Relaxed Polar Codes under AWGN Channels with Low Complexity and Low Latency

2019 ◽  
Author(s):  
Xinyi Wang ◽  
Ce Sun ◽  
Jingxuan Huang ◽  
Dai Jia ◽  
Yifan Jiang ◽  
...  
Keyword(s):  
Low Complexity ◽  
Low Latency ◽  
Polar Codes

scholarly journals Flexible soft-output decoding of polar codes

2021 ◽  
Vol 2021 (1) ◽  
Author(s):  
Sunghoon Lee ◽  
Jooyoun Park ◽  
Il-Min Kim ◽  
Jun Heo
Keyword(s):  
Belief Propagation ◽  
Low Complexity ◽  
Low Latency ◽  
Polar Codes ◽  
High Complexity ◽  
Decoding Algorithms ◽  
Long Latency ◽  
System Requirement ◽  
System Requirements ◽  
High Computational Complexity

AbstractIn this research, we study soft-output decoding of polar codes. Two representative soft-output decoding algorithms are belief propagation (BP) and soft cancellation (SCAN). The BP algorithm has low latency but suffers from high computational complexity. On the other hand, the SCAN algorithm, which is proposed for reduced complexity of soft-output decoding, achieves good decoding performance but suffers from long latency. These two algorithms are suitable only for two extreme cases that need very low latency (but with high complexity) or very low complexity (but with high latency). However, many practical systems may need to work for the moderate cases (i.e., not too high latency and not too high complexity) rather than two extremes. To adapt to the various needs of the systems, we propose a very flexible soft-output decoding framework of polar codes. Depending on which system requirement is most crucial, the proposed scheme can adapt to the systems by controlling the level of parallelism. Numerical results demonstrate that the proposed scheme can effectively adapt to various system requirements by changing the level of parallelism.

SDR-Based Precoding for Multi-User Multi-Stream MIMO Downlinks

2014 ◽  
Vol 543-547 ◽  
pp. 2004-2008
Author(s):  
Xin Min Li ◽  
Bao Ming Bai ◽  
Juan Zhao
Keyword(s):  
Bit Error Rate ◽  
Optimization Problem ◽  
Optimization Theory ◽  
Threshold Value ◽  
Low Complexity ◽  
Semidefinite Programs ◽  
Single Antenna ◽  
Simulation Results ◽  
Quadratically Constrained ◽  
Ber Performance

The existing methods based on convex-optimization theory, which use the concept of SINR, can just design the optimal precoder for each user with single antenna. In this paper, we design the optimal precoding matrices for multi-user MIMO downlinks by solving the optimization problem that minimizes total transmit power subject to signal-leakage-plus-noise-ratio (SLNR) constraints. Because SLNR of each user is determined by its own precoding matrix and is independent of other users, the goal problem can be separated into a series of decoupled low-complexity quadratically constrained quadratic programs (QCQPs). Using the semidefinite relaxation (SDR) technique, these QCQPs can be reformulated into the semidefinite programs (SDP) and be solved effectively. Simulation results show that proposed precoding scheme is quite feasible when each user has two receive antennas, and it has better bit error rate (BER) performance than the original maximal-SLNR precoding scheme when SLNR of each user satisfies large threshold value.

LOW POWER FULL SEARCH BLOCK MATCHING MOTION ESTIMATION VLSI ARCHITECTURES

2004 ◽  
Vol 13 (06) ◽  
pp. 1271-1288 ◽  
Author(s):  
MOHAMED A. ELGAMEL ◽  
MAGDY A. BAYOUMI ◽  
AHMED M. SHAMS ◽  
BERTRAND ZAVIDOVIQUE
Keyword(s):  
Power Consumption ◽  
Motion Estimation ◽  
Low Power ◽  
Block Matching ◽  
Huge Amount ◽  
Analytical Analysis ◽  
Vlsi Architectures ◽  
Simulation Results ◽  
Full Search ◽  
Low Power Architectures

Power consumption is very critical for portable video applications. During compression, the motion estimation unit consumes the largest portion of power since it performs a huge amount of computation. Different low power architectures for implementing the full-search block-matching (FSBM) motion estimation are discussed. Also, architectural enhancements to further reduce the power consumed during FSBM motion estimation without sacrificing throughput or optimality are presented. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between the different architectures including our enhancements and others is presented using simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements.

Sign in / Sign up

Export Citation Format

Share Document