In recent years, self-heating has become a significant issue in the performance of emerging ultra-scaled microelectronics. This is a particular problem in emerging finFET designs because of the use of thick buried oxide layers which impede heat flow to the heat sink. Furthermore, leakage power is becoming an increasingly important contributor to total power dissipation in deep sub-micron technology. Sub-threshold leakage, a component of leakage power, scales exponentially with temperature, leading to the possibility of thermal runaway. In this paper, compact thermal models of logic gates are developed for use in floor-plan electrical models of VLSI circuits. Concurrent electro-thermal simulation of the floor plan temperature and total power is then used to evaluate the possibility of thermal runaway in benchmark circuits. It is found that thermal runaway can occur with finFETs using 28 nm technology at the ITRS specified sub-threshold leakage (150 nA/μm) at a principal input activity of 0.5.
