The Evaluation of Error Detection Probability at the Outputs of Combinational Circuits Under Concurrent Error Detection on the Basis of Summation Codes

2018 ◽  
Author(s):  
Dmitry Efanov ◽  
Valery Sapozhnikov ◽  
Vladimir Sapozhnikov ◽  
Dmitry Plotnikov
Keyword(s):  
Error Detection ◽  
Detection Probability ◽  
Concurrent Error Detection ◽  
Combinational Circuits

DESIGN FLOW OF CONCURRENT ERROR DETECTION SCHEMES FOR COMBINATIONAL CIRCUITS

2018 ◽  
Vol 65 ◽  
pp. 92-98
Author(s):  
A. L. Stempkovskiy ◽  
◽  
D. V. Telpukhov ◽  
A. I. Demeneva ◽  
T. D. Zhukova ◽  
...  
Keyword(s):  
Error Detection ◽  
Design Flow ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Schemes

scholarly journals Organization of Combinational Circuits Concurrent Error Detection Systems Based on the Modified Code with Summation of Weighted Transitions.

2016 ◽  
Vol 38 (1) ◽  
pp. 87-98
Author(s):  
V.V. SAPOZHNIKOV ◽  
◽  
VL.V. SAPOZHNIKOV ◽  
D.V. EFANOV ◽  
V.V. DMITRIEV ◽  
...  
Keyword(s):  
Error Detection ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Systems

scholarly journals On VHDL synthesis of self-checking two-level combinational circuits

2004 ◽  
Vol 17 (1) ◽  
pp. 69-79
Author(s):  
Tatjana Stankovic ◽  
Mile Stojcev ◽  
Goran Djordjevic
Keyword(s):  
Error Detection ◽  
Data Integrity ◽  
Operating Speed ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Combinational Circuits ◽  
Combinational Circuit ◽  
The Third ◽  
Separable Code

Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.

Application of constant-weight code "1-out-if-5" for the organization of combinational circuits check

2017 ◽  
pp. 307-319
Author(s):  
Valeriy Sapozhnikov ◽  
Vladimir Sapozhnikov ◽  
Dmitriy Efanov ◽  
Dmitriy Pyvovarov
Keyword(s):  
Error Detection ◽  
Practical Importance ◽  
Discrete Systems ◽  
Code Word ◽  
Technical Diagnostics ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Constant Weight ◽  
Testing Patterns ◽  
Full Check

Objective: To study specificities of “1-out of-5”equilibrium code application in the process of concurrent error detection of combinational logic circuits organization. Methods: Information and coding theories, as well as technical diagnostics of discrete systems were applied. Results: It was suggested to apply a “1-out of-5”equilibrium code in organizing of combinational circuits control by means of Boolean complement method, the tester of which has a simple structure and needs five testing patterns for its full check. The calculation method of Boolean complement functions was given; the former makes it possible to provide testability of a Boolean complement block and a tester within a checking circuit. The advantages of a “1-out of-5”equilibrium code application were presented, compared to the usage of other equilibrium codes with a shorter length of a code word for organization of combinational circuits’ check. Practical importance: The application of a “1-out of-5”equilibrium code for organization of combinational circuits’ check is promising for self-checking discrete automatic and calculating machines.

The features of the concurrent error-detection systems of combinational logic circuits based on the search for groups of symmetrically-independent outputs construction

2020 ◽  
Vol 6 (4) ◽  
pp. 532-549
Author(s):  
V. V. Sapozhnikov ◽  
◽  
Vl. V. Sapozhnikov ◽  
D. V. Efanov ◽  
◽  
...  
Keyword(s):  
Internal Structure ◽  
Error Detection ◽  
Logic Circuits ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Combinational Circuits ◽  
Detection Systems ◽  
Combinational Logic Circuits ◽  
Berger Codes

The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented

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