Application of constant-weight code "1-out-if-5" for the organization of combinational circuits check

2017 ◽  
pp. 307-319
Author(s):  
Valeriy Sapozhnikov ◽  
Vladimir Sapozhnikov ◽  
Dmitriy Efanov ◽  
Dmitriy Pyvovarov
Keyword(s):  
Error Detection ◽  
Practical Importance ◽  
Discrete Systems ◽  
Code Word ◽  
Technical Diagnostics ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Constant Weight ◽  
Testing Patterns ◽  
Full Check

Objective: To study specificities of “1-out of-5”equilibrium code application in the process of concurrent error detection of combinational logic circuits organization. Methods: Information and coding theories, as well as technical diagnostics of discrete systems were applied. Results: It was suggested to apply a “1-out of-5”equilibrium code in organizing of combinational circuits control by means of Boolean complement method, the tester of which has a simple structure and needs five testing patterns for its full check. The calculation method of Boolean complement functions was given; the former makes it possible to provide testability of a Boolean complement block and a tester within a checking circuit. The advantages of a “1-out of-5”equilibrium code application were presented, compared to the usage of other equilibrium codes with a shorter length of a code word for organization of combinational circuits’ check. Practical importance: The application of a “1-out of-5”equilibrium code for organization of combinational circuits’ check is promising for self-checking discrete automatic and calculating machines.

DESIGN FLOW OF CONCURRENT ERROR DETECTION SCHEMES FOR COMBINATIONAL CIRCUITS

2018 ◽  
Vol 65 ◽  
pp. 92-98
Author(s):  
A. L. Stempkovskiy ◽  
◽  
D. V. Telpukhov ◽  
A. I. Demeneva ◽  
T. D. Zhukova ◽  
...  
Keyword(s):  
Error Detection ◽  
Design Flow ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Schemes

scholarly journals Organization of Combinational Circuits Concurrent Error Detection Systems Based on the Modified Code with Summation of Weighted Transitions.

2016 ◽  
Vol 38 (1) ◽  
pp. 87-98
Author(s):  
V.V. SAPOZHNIKOV ◽  
◽  
VL.V. SAPOZHNIKOV ◽  
D.V. EFANOV ◽  
V.V. DMITRIEV ◽  
...  
Keyword(s):  
Error Detection ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Systems

scholarly journals Review of the book «Proceedings on the Self-Checking Embedded Control Circuits Synthesis Theory Based on Binary Redundant Codes»

2021 ◽  
Vol 19 (2) ◽  
pp. 140-143
Author(s):  
A. Yu. Matrosova
Keyword(s):  
Computer Technology ◽  
Error Detection ◽  
Discrete Systems ◽  
The Self ◽  
Binary Codes ◽  
Technical Diagnostics ◽  
Embedded Control ◽  
Polynomial Codes ◽  
Control Circuits ◽  
Berger Codes

Proceedings on the Self-Checking Embedded Control Circuits Synthesis Theory Based on Binary Redundant Codes. Vol. 1. Moscow, Nauka publ., 2020, 611 p. ISBN 978-5-02-040758-9.Proceedings on the Self-Checking Embedded Control Circuits Synthesis Theory Based on Binary Redundant Codes. Vol. 2. Moscow, Nauka publ., 2021, 527 p. ISBN 978-5-02-040757-2.The first volume of the book includes papers devoted to three main areas of research in the field of synthesis of self-checking discrete systems: study of features of classical sum codes (Berger codes), modular sum codes, as well as their modifications proposed by the authors of the articles; study of features of codes for which check bits are obtained using convolutions modulo М = 2 of a part of data bits (polynomial codes and classical Hamming codes); research of the Boolean Complement method for organisation of self-checking discrete systems based on redundant binary codes. Materials are provided on detailed characteristics of error detection in data bits of redundant binary codes under the condition of errorfree check bits, descriptions of methods for constructing previously unknown modified sum codes and features of methods for synthesizing self-checking discrete systems based on binary redundant codes.The second volume of the book includes papers in the field of constructing binary sum codes weighted bits and transitions between bits occupying adjacent positions in data vectors of code words, as well as the results of studying their characteristics and methods of synthesising coding equipment. The issues of application of features of codes in organisation of self-checking discrete systems are considered. The reader will find on the pages of this volume materials on detailed characteristics of error detection in data bits of weight-based sum codes provided that the check bits are error-free, descriptions of methods for constructing previously unknown weight-based sum codes and features of methods for synthesising self-checking discrete systems based on them.The book can be useful for developers, researchers and engineers working in the field of technical diagnostics of discrete systems and synthesis of systems with fault detection, as well as students studying computer science, computer technology and automation. 

scholarly journals On VHDL synthesis of self-checking two-level combinational circuits

2004 ◽  
Vol 17 (1) ◽  
pp. 69-79
Author(s):  
Tatjana Stankovic ◽  
Mile Stojcev ◽  
Goran Djordjevic
Keyword(s):  
Error Detection ◽  
Data Integrity ◽  
Operating Speed ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Combinational Circuits ◽  
Combinational Circuit ◽  
The Third ◽  
Separable Code

Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.

The Concurrent Error-Detection Systems Organization Based on the Boolean Complement Method with the Preliminary Transformation of Operating Functions into Check Vectors of Berger Codes

2021 ◽  
Vol 27 (6) ◽  
pp. 306-313
Author(s):  
D. V. Efanov ◽  
◽  
V. V. Saposhnikov ◽  
Vl. V. Saposhnikov ◽  
◽  
...  
Keyword(s):  
Error Detection ◽  
Concurrent Error Detection ◽  
Structural Redundancy ◽  
Compression Scheme ◽  
Digital Device ◽  
Constant Weight ◽  
Detection Systems ◽  
Detection Characteristics ◽  
Berger Codes

The article describes a new way of concurrent error-detection (CED) systems organization using the Boolean complement method, which involves the use of pre-compression of signals from the diagnostic object using encoders of classical sum codes (Berger codes). Control of compressed signals is carried out using the constant-weight "1-out-of-4" code. In comparison with the known methods of the CED systems organization, it is possible to implement a self-checking digital device using one such circuit, and this significantly reduces the structural redundancy. The article suggests using the encoders of modified Berger codes with improved error detection characteristics as a compression scheme.

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