scholarly journals On VHDL synthesis of self-checking two-level combinational circuits

2004 ◽  
Vol 17 (1) ◽  
pp. 69-79
Author(s):  
Tatjana Stankovic ◽  
Mile Stojcev ◽  
Goran Djordjevic
Keyword(s):  
Error Detection ◽  
Data Integrity ◽  
Operating Speed ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Combinational Circuits ◽  
Combinational Circuit ◽  
The Third ◽  
Separable Code

Concurrent error detection (CED) is an important technique in the design of system in which dependability and data integrity are important. Using the separable code for CED has the advantage that no decoding is needed to get the normal output bits. In this paper, we address the problem of synthesizing totally self-checking two level combinational circuits starting from a VHDL description. Three schemes for CED are proposed. The first scheme uses duplication of a combinational logic with the addition of a totally self-checking comparator. The second scheme for synthesizing combinational circuits with CED uses Bose-Lin code. The third scheme is based on parity codes on the outputs of a combinational circuit. The area overheads and operating speed decreases for seven combinational circuits of standard architecture are reported in this paper.

The specificities of organization of concurrent error detection systems for combinational circuits based on polynomial codes

2018 ◽  
pp. 432-445
Author(s):  
Valeriy Sapozhnikov ◽  
Vladimir Sapozhnikov ◽  
Dmitriy Efanov ◽  
Ruslan Abdullaev
Keyword(s):  
Error Detection ◽  
Logic Circuits ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Computer Engineering ◽  
Combinational Circuit ◽  
Detection Systems ◽  
Essential Properties ◽  
Combinational Logic Circuits ◽  
Polynomial Codes

Objective: To study the specificities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.

The features of the concurrent error-detection systems of combinational logic circuits based on the search for groups of symmetrically-independent outputs construction

2020 ◽  
Vol 6 (4) ◽  
pp. 532-549
Author(s):  
V. V. Sapozhnikov ◽  
◽  
Vl. V. Sapozhnikov ◽  
D. V. Efanov ◽  
◽  
...  
Keyword(s):  
Internal Structure ◽  
Error Detection ◽  
Logic Circuits ◽  
Concurrent Error Detection ◽  
Combinational Logic ◽  
Combinational Circuits ◽  
Detection Systems ◽  
Combinational Logic Circuits ◽  
Berger Codes

The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented

DESIGN FLOW OF CONCURRENT ERROR DETECTION SCHEMES FOR COMBINATIONAL CIRCUITS

2018 ◽  
Vol 65 ◽  
pp. 92-98
Author(s):  
A. L. Stempkovskiy ◽  
◽  
D. V. Telpukhov ◽  
A. I. Demeneva ◽  
T. D. Zhukova ◽  
...  
Keyword(s):  
Error Detection ◽  
Design Flow ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Schemes

scholarly journals Organization of Combinational Circuits Concurrent Error Detection Systems Based on the Modified Code with Summation of Weighted Transitions.

2016 ◽  
Vol 38 (1) ◽  
pp. 87-98
Author(s):  
V.V. SAPOZHNIKOV ◽  
◽  
VL.V. SAPOZHNIKOV ◽  
D.V. EFANOV ◽  
V.V. DMITRIEV ◽  
...  
Keyword(s):  
Error Detection ◽  
Concurrent Error Detection ◽  
Combinational Circuits ◽  
Detection Systems

Full Error Detection and Correction Method Applied on Pipelined Structure Using Two Approaches

2020 ◽  
Vol 29 (13) ◽  
pp. 2050218 ◽  
Author(s):  
Mehmed Dug ◽  
Stefan Weidling ◽  
Egor Sogomonyan ◽  
Dejan Jokic ◽  
Milos Krstic
Keyword(s):  
Error Detection ◽  
Soft Errors ◽  
Correction Method ◽  
Soft Error ◽  
Combinational Logic ◽  
Combinational Circuit ◽  
Multiple Faults ◽  
Error Detection And Correction ◽  
Detection Circuit ◽  
The One

In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.

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