Debug methodology for arithmetic circuits on FPGAs

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings. ◽

10.1109/fpt.2002.1188687 ◽

2003 ◽

Author(s):

M. Kubo ◽

M. Fujita

Keyword(s):

Arithmetic Circuits

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Active Learning Methods Applied in the Course “Digital Electronics” on the Topic “Arithmetic Circuits Using FPGA Design”

2019 29th Annual Conference of the European Association for Education in Electrical and Information Engineering (EAEEIE) ◽

10.1109/eaeeie46886.2019.9000421 ◽

2019 ◽

Author(s):

Adriana Borodzhieva ◽

Iordan Stoev ◽

Valentin Mutkov

Keyword(s):

Active Learning ◽

Arithmetic Circuits ◽

Fpga Design ◽

Learning Methods ◽

Digital Electronics

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On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

Journal of Electronic Testing ◽

10.1007/s10836-020-05858-5 ◽

2020 ◽

Vol 36 (1) ◽

pp. 33-46

Author(s):

B. Deveautour ◽

A. Virazel ◽

P. Girard ◽

V. Gherman

Keyword(s):

Error Detection ◽

Arithmetic Circuits ◽

Approximate Computing ◽

Detection Scheme

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Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2021.3059924 ◽

2021 ◽

pp. 1-1

Author(s):

Akira Ito ◽

Rei Ueno ◽

Naofumi Homma

Keyword(s):

Formal Verification ◽

Galois Field ◽

Arithmetic Circuits

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Nonconventional Computer Arithmetic Circuits, Systems and Applications

IEEE Circuits and Systems Magazine ◽

10.1109/mcas.2020.3027425 ◽

2021 ◽

Vol 21 (1) ◽

pp. 6-40

Author(s):

Leonel Sousa

Keyword(s):

Computer Arithmetic ◽

Arithmetic Circuits

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Efficient binary to quaternary and vice versa converters: embedding in quaternary arithmetic circuits

The Journal of Supercomputing ◽

10.1007/s11227-021-03696-6 ◽

2021 ◽

Author(s):

Abdollah Norouzi Doshanlou ◽

Majid Haghparast ◽

Mehdi Hosseinzadeh ◽

Midia Reshadi

Keyword(s):

Arithmetic Circuits

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Error detection of arithmetic circuits using a residue checker with signed-digit number system

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dftvs.2001.966754 ◽

2002 ◽

Author(s):

Shugang Wei ◽

Kensuke Shimizu

Keyword(s):

Error Detection ◽

Number System ◽

Arithmetic Circuits ◽

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A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368656 ◽

2000 ◽

Author(s):

Taewhan Kim ◽

Junhyung Um

Keyword(s):

Arithmetic Circuits ◽

Short Paper ◽

Carry Save Adders

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Arithmetic Circuits Verification without Looking for Internal Equivalences

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design ◽

10.1109/memcod.2008.4547681 ◽

2008 ◽

Author(s):

O. Sarbishei ◽

B. Alizadeh ◽

Masahiro Fujita

Keyword(s):

Arithmetic Circuits

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Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction

2017 IEEE International Conference on Computer Design (ICCD) ◽

10.1109/iccd.2017.37 ◽

2017 ◽

Author(s):

Farimah Farahmandi ◽

Prabhat Mishra

Keyword(s):

Arithmetic Circuits ◽

Automated Debugging ◽

Basis Reduction ◽

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Arithmetic Circuits

Introduction to Logic Circuits & Logic Design with Verilog ◽

10.1007/978-3-030-13605-5_12 ◽

2019 ◽

pp. 397-426

Author(s):

Brock J. LaMeres

Keyword(s):

Arithmetic Circuits

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