On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

2020 ◽  
Vol 36 (1) ◽  
pp. 33-46
Author(s):  
B. Deveautour ◽  
A. Virazel ◽  
P. Girard ◽  
V. Gherman
Keyword(s):  
Error Detection ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Detection Scheme

scholarly journals An Efficient Hardware-Based Fault-Tolerant Method for SMS4

2018 ◽  
Vol 208 ◽  
pp. 02005
Author(s):  
Hanguang Luo ◽  
Guangjun Wen ◽  
Jian Su
Keyword(s):  
Error Detection ◽  
Wireless Lan ◽  
Fault Tolerant ◽  
Low Cost ◽  
Primary Objective ◽  
Data Confidentiality ◽  
Detection Scheme ◽  
Detection Delay ◽  
Encryption Decryption ◽  
Online Error Detection

The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.

Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits

2003 ◽  
Vol 12 (01) ◽  
pp. 41-53 ◽  
Author(s):  
Shugang Wei ◽  
Kensuke Shimizu
Keyword(s):  
Real Time ◽  
Error Detection ◽  
Binary Tree ◽  
Word Length ◽  
Arithmetic Circuits ◽  
Binary Number ◽  
Residue Number ◽  
Residue Arithmetic ◽  
Large Product ◽  
Binary Tree Structure

This paper presents a fast residue checker for the error detection of arithmetic circuits. The residue checker consists of a number of residue arithmetic circuits such as adders, multipliers and binary-to-residue converters based on radix-two signed-digit (SD) number arithmetic. The proposed modulo m (m = 2p ± 1) adder is designed with a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. The modulo m multiplier and binary-to-residue number converter are constructed with a binary tree structure of the modulo m SD adders. Thus, the modulo m multiplication is performed in a time proportional to log 2 p and an n-bit binary number is converted into a p-digit SD residue number, n ≫ p, in a time proportional to log 2(n/p). By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.

scholarly journals Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection

2019 ◽  
Vol 9 (2) ◽  
pp. 17 ◽  
Author(s):  
Roberto Giorgio Rizzo ◽  
Andrea Calimera
Keyword(s):  
Error Detection ◽  
Real Life ◽  
Cmos Technology ◽  
Approximate Computing ◽  
Noise Tolerance ◽  
Detection Mechanism ◽  
Quality Of Results ◽  
Timing Speculation ◽  
Open Issue

Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.

Sign in / Sign up

Export Citation Format

Share Document