Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit

2005 ◽  
Author(s):  
Jong-Kil Shin ◽  
Tae-Whan Yoo ◽  
Man-Seop Lee
Keyword(s):  
Logic Gates ◽  
Current Mode ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase ◽  
Current Mode Logic

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase

1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

2013 ◽  
Vol 7 (3) ◽  
pp. 159-168 ◽  
Author(s):  
Sangjin Byun ◽  
Chung Hwan Son ◽  
Jongil Hwang ◽  
Byung‐Hun Min ◽  
Mun‐Yang Park ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase ◽  
Phase Offset ◽  
Static Phase ◽  
Static Phase Offset

A 1/4-RATE LINEAR PHASE DETECTOR FOR HIGH SPEED PLL-BASED CLOCK AND DATA RECOVERY CIRCUIT

2014 ◽  
Vol 23 (05) ◽  
pp. 1450072 ◽  
Author(s):  
SOMAYEH ADIBIFARD ◽  
SEYYED HASSAN MOUSAVI ◽  
SOHEYL ZIABAKHSH ◽  
MUSTAPHA C. E. YAGOUB
Keyword(s):  
Power Consumption ◽  
Delay Time ◽  
High Speed ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase ◽  
Lower Power ◽  
Reference Signals

A novel 1/4-rate clock phase detector (PD) structure for phase locked loop (PLL)-based clock and data recovery (CDR) is proposed. In this topology, the retimed data is generated within the circuit and no extra circuit is required. Furthermore, the error and reference signals are independent of delay time through gates and thus, no extra replica circuit is needed to compensate such delay. Designed in a 0.18-μm CMOS technology, the proposed 10 Gb/s PD consumes 30 mA from a 1.8 V supply, resulting in a lower power consumption for high-speed applications compared to conventional topologies.

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