Design and simulation of FPGA based all digital phase locked loop (ADPLL)

2017 3rd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT) ◽

10.1109/icatcct.2017.8389144 ◽

2017 ◽

Author(s):

Shruti Edway ◽

R K Manjunath

Keyword(s):

Phase Locked Loop ◽

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Digital Phase-Locked Loop Based on FIR Filters

International Conference Image Processing, Computers and Industrial Engineering (ICICIE'2014) Jan. 15-16, 2014 Kuala Lumpur (Malaysia) ◽

10.15242/iie.e0114564 ◽

2014 ◽

Keyword(s):

Phase Locked Loop ◽

Fir Filters ◽

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DESIGN OF ALL DIGITAL PHASE LOCKED LOOP (D-PLL) WITH FAST ACQUISITION TIME

International Journal of Research in Engineering and Technology ◽

10.15623/ijret.2013.0212089 ◽

2013 ◽

Vol 02 (12) ◽

pp. 536-539

Author(s):

Bharath Reddy.M .

Keyword(s):

Phase Locked Loop ◽

Acquisition Time ◽

Digital Phase ◽

Fast Acquisition

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Digital Phase Locked Loop with Broad Lock Range using Chaos Control Technique

Intelligent Automation & Soft Computing ◽

10.1080/10798587.2006.10642924 ◽

2006 ◽

Vol 12 (2) ◽

pp. 183-187 ◽

Author(s):

Qassim Nasir

Keyword(s):

Chaos Control ◽

Phase Locked Loop ◽

Control Technique ◽

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A 23-30.8GHz All-digital Phase-Locked Loop for 5G Communication System

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278314 ◽

2020 ◽

Author(s):

Jieyang Li ◽

Ting Yi ◽

Zhiliang Hong

Keyword(s):

Communication System ◽

Phase Locked Loop ◽

Digital Phase ◽

5G Communication

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Design and Construction of a Low Cost All-Digital Phase Locked Loop Based on Field Programmable Gate Array

Journal of Physics Conference Series ◽

10.1088/1742-6596/1972/1/012054 ◽

2021 ◽

Vol 1972 (1) ◽

pp. 012054

Author(s):

Chunyu Zhang ◽

Shouxiang Wang ◽

Ruxun He ◽

Qianyu Zhao ◽

Kai Wang

Keyword(s):

Field Programmable Gate Array ◽

Low Cost ◽

Phase Locked Loop ◽

Digital Phase ◽

Field Programmable ◽

Design And Construction

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A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur

2019 Symposium on VLSI Circuits ◽

10.23919/vlsic.2019.8778010 ◽

2019 ◽

Author(s):

Ji-Hwan Seol ◽

Dennis Sylvester ◽

David Blaauw ◽

Taekwang Jang

Keyword(s):

Phase Locked Loop ◽

Digital Phase ◽

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A novel phase detection system for linear all-digital phase locked loop

2012 Students Conference on Engineering and Systems ◽

10.1109/sces.2012.6199080 ◽

2012 ◽

Author(s):

Abhishek Das ◽

Suraj Dash ◽

B. Chitti Babu ◽

Ajit Kumar Sahoo

Keyword(s):

Detection System ◽

Phase Locked Loop ◽

Phase Detection ◽

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A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2017.2776313 ◽

2018 ◽

Vol 53 (1) ◽

pp. 50-65 ◽

Author(s):

Taekwang Jang ◽

Seokhyeon Jeong ◽

Dongsuk Jeon ◽

Kyojin David Choo ◽

Dennis Sylvester ◽

...

Keyword(s):

Phase Locked Loop ◽

Switched Capacitor ◽

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A Digital Phase Locked Loop for Nakagami-m fading channels using QPSK modulation scheme

2012 2nd National Conference on Computational Intelligence and Signal Processing (CISP) ◽

10.1109/nccisp.2012.6189695 ◽

2012 ◽

Author(s):

Basab B Purkayastha ◽

Kandarpa Kumar Sarma

Keyword(s):

Fading Channels ◽

Phase Locked Loop ◽

Modulation Scheme ◽

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Performance of a First-Order Transition Sampling Digital Phase-Locked Loop Using Random-Walk Models

IRE Transactions on Communications Systems ◽

10.1109/tcom.1972.1091141 ◽

1972 ◽

Vol 20 (2) ◽

pp. 119-131 ◽

Author(s):

J. Holmes

Keyword(s):

Random Walk ◽

Phase Locked Loop ◽

Order Transition ◽

First Order ◽

Digital Phase ◽

First Order Transition

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