3D microelectronics integration and wafer scale packaging promise improvements in functional density and cost compared to conventional 2D microelectronics and packaging technologies. The realization of these improvements will require further adoption of 3D volume manufacturing process technologies. These process technologies will likely include through silicon via (TSV) and die or wafer bonding with and without 3D interconnect. Low temperature direct bond technologies have a number of inherent performance and cost advantages compared to other bonding technologies. This paper describes low temperature direct oxide bond technologies with and without a scalable 3D interconnect developed by Ziptronix and cost savings, performance and applications that will be enabled by adoption of these technologies. Enabled cost savings and performance include system or network-on-chip, system in package, and TSVs. Enabled applications include backside illuminated image sensors, micron-scale pitch vertically integrated image sensor arrays, 3D system-on-chip and 3D network-on-chip.
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
