Ultra-low Residue Flux Applications in RF Front-End Packages

With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

Optimization of High-Speed Electrolytic Plating of Copper Pillar to Achieve a Flat Top Morphology and Height Uniformity

Cu plating bath for high-speed electrodeposition of Cu pillar was designed in consideration of a flat top morphology of pillar and a pillar height uniformity. An ideal polarization curve was assumed for the flat top morphology. To obtain the ideal polarization curve, an effect of organic additive concentration and solution agitation on the polarization curve were investigated. The basic bath components were optimized considering a Wagner number to improve pillar height uniformity. To confirm the pillar top morphology and the pillar height uniformity, a 300 mm diameter wafer was plated with Cu at 20 A/dm2. As a result, improved pillar top morphology and pillar height uniformity were obtained. The optimized plating bath was applied to the plating of large-size panel of 415 × 510 mm.

Optical Data Link Module for Data Transmission in Smart Catheters

We demonstrate a stand-alone optical data link module (ODLM) that fits in the limited space budget of smart imaging catheters. The module is based on an extension of the Flex-to-Rigid (F2R) technology platform for miniaturized system integration. The ODLM is a silicon-based interposer that comprises a commercially available Vertical Cavity Surface Emitting Laser (VCSEL), which has its electrical contacts and laser emitting spot on the same surface. With the flexible interconnects, the ODLM reroutes the flip-chipped VCSEL electrical contacts to the side that is perpendicular to the surface of the VCSEL. This enables the ODLM to be mounted on a flex-PCB and fit into the limited space in the distal tip of the smart catheter. An optical fiber that runs in parallel to the catheter shaft is inserted into the through-silicon hole (TSH) of the ODLM and self-aligned to the VCSEL for optical data transmission. The design of the ODLM and the F2R technology platform are introduced, and an ODLM demonstrator is fabricated and presented.

Plasma Surface Engineering: An Enabling Technology Designed to Clean and Protect Printed Circuit Boards

Long term reliability and performance of printed circuit boards (PCBs) are strongly affected by the presence of surface contaminants from the manufacturing and assembly processes. Flux and solder residue, dust particles, oils and greases are often found on the assembled boards and can inhibit the successful application of conformal coatings that are used to protect the electronic components. Surface contaminants can cause coating delamination, dendritic growth, electromigration, corrosion and result in compromised coatings. In the first part of this paper, the fundamental mechanism of plasma-induced removal of organic contaminants from PCBs will be presented. While vacuum based plasmas are considered the traditional solvent-free technology for surface cleaning, a new approach involving air plasma operating under atmospheric pressure conditions is gaining interest due to its adaptability for industrial inline processing. The low concentration of oxygen that is available in the plasma gas is effective in vaporizing organic contaminants leaving behind a clean surface. Additionally, atmospheric plasma processes focusing on the development of functional nanocoatings on PCBs have been investigated. These plasma-enhanced chemical vapor deposition (PECVD) processes involve the delivery and vaporization of small volumes of solvent-free precursors that react with the plasma to form thin coatings on polymer substrates. Depending on the chemical structure of the precursor used, adhesion promoting, water repellant or electrical barrier coatings of 30–100nm thickness can be deposited. These protective functional coatings do not require any curing or special handling and no chemical waste is generated. The latest developments in atmospheric pressure PECVD for electronics protection will be presented in the second part of the paper. Besides the improvement of device performance and reliability, the application of PECVD has the potential to replace chemical substances such as primers known to have harmful impact on human health and the environment.

Enhancement of ESD performances of Silicon Capacitors for RFID solutions

Radio-Frequency IDentification devices such as smart cards and RFID tags are based on the presence of a resonant tuned LC circuit associated to the RFID Integrated Circuit (IC). The use of discrete capacitor, external to the IC gives greater flexibility and design freedom. In the race of miniaturization, manufacturers of RFID devices always require smaller electronic components. To save space and in the same time improve performances, capacitors are exposed to height and volume constraints. In the same time, the capacitor has to withstand ESD stresses that can occur during the assembly of the device and during operation. Murata has developed a unique thin capacitor technology in silicon. This paper reports the development of a range of low profile capacitors with enhanced ESD performances. The manufacturing process optimization and the design adjustments will be presented here. The process was optimized by taking into account the main electrical parameters: leakage current, breakdown voltage, capacitance density, capacitance accuracy, Equivalent Series Resistance (ESR) and Self-Resonant Frequency (SRF). The dielectric stack was defined in order to integrate up to 330pF in 0402 case. The process architecture, based on accurate planar capacitor with thick dielectric will be discussed. With this architecture there is no constraint to reach low thickness, such as 100μm or even lower. The ESD threshold of each Silicon Capacitor was investigated with design variations associated to Human Body Model measurements. A Single Project Wafer (SPW) was founded with 36 different capacitor designs. Design modulations specifically addressed the orientation and position of the contacts openings. Special care was taken to maximize the width of the contact holes and metal tracks. A mosaic approach, constructed out of a massive network of parallelized elementary cells was also implemented, so that the charges of the ESD pulse do not concentrate at the same place, leading to electrical failure. Examples of defects due to ESD stress will be shown with failure analysis cross-sections and ways to enhance the ESD threshold by design will be illustrated.

Reliability Simulation of Cu/Polymer interface in Fan-out Wafer Level Packaging

In order to improve the performance and reliability of the package, the interlayer dielectric (Polymer) must not be delaminated and materials should not fracture due to thermal stresses during the operation or the manufacturing process. If the reliability of the package can be known in advance by simulation, it can be expected to greatly help in material selection and package design. Firstly, we created material-specific master curves (time–temperature superposition) by considering the measurement results of the Peel Test at the Cu/Polymer interface and the mechanical properties of polymer. The critical Energy Release Rate (𝒢𝒸) could be calculated by its master curve. Secondary, we calculated the Energy Release Rate (𝒢) from Finite Element Analysis (FEA) in the package model structure. Finally, delamination is judged by normalizing 𝒢/𝒢𝒸. This study has made it possible to simulate the delamination possibility of Cu/Polymer interface at arbitrary temperatures and displacement rates from basic material data and FEA analysis of the package model structure.

Acceleration Factors and Life Predictions

Acceleration factors (AF) are key to designing an effective accelerated life test (ALT). They represent the ratio of the time in field to the time in test for a particular event to occur (typically a failure event related to a specific failure mechanism). Time to failure for a device generally correlates with the amount of stress applied (the higher the stress, the quicker the device will fail), and failure models exist to mathematically define that correlation for various failure mechanisms. This allows for use of a higher stress in test than in the field, thereby providing an acceleration factor that shortens the time in test to demonstrate a failure-free time period. ALT can take the form of qualitative or quantitative testing. The latter is used to determine the life characteristics of the device with some reliability and confidence level. Usage rate acceleration and higher stress acceleration can be used. It is important to consider the design limits of the device based on its specification and material properties, and limit the stress levels in test so as not to induce failure mechanisms that the device would not otherwise have experienced in the field. ALT results are used to make life predictions for the device tested. With no failures, the test results demonstrate the required reliability and confidence level metrics for the failure mechanism of interest. With several failures, a reliability software tool can be used with the appropriate analysis method, rank method, and confidence bounds method chosen in order to extrapolate to an expected life in test. The equivalent field life is based on multiplying the expected life in test by the AF. If the field stress and/or test stress are not constant, there are multiple acceleration factors to utilize. As a result, an equivalent acceleration factor needs to be calculated and used as the AF when predicting equivalent field life.

Electromigration in Power Devices

In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Methodology to Quantify Impact of Package Delamination on Performance of High-Side Smart Power Switch Design

Generally, IC packages with exposed pads have excellent thermal and electrical performance – assuming high fidelity and integrity of die attach material. However, reliability challenges associated with die attach impacts electrical performance of vertical power FETs for high-side power switches. As such, it is critical to quantify the impact of these challenges on high-side power switches operation, so that their protection and diagnostic feature circuitries can be properly designed for mission critical applications. In this paper we present on a package and PCB co-modeling methodology that was developed to assess impact of die attach integrity on performance of high-side power switch designs. We explain how electrical co-optimization of the system (viz. FET-Package-PCB) interactions, was achieved through a coupled circuit-to-electromagnetic modeling, simulation, and analysis methodology. Silicon laboratory measurements data that validate the modeling methodology will be presented.

Construction Kit of RF-Blocks in Package Technologies

Advanced packages are necessary to cope with the requirements of 5G and radar technologies with 60 GHz and beyond. For proper RF design with rising package technology requirements demands for usage of predefined structures with predefined layout elements, manufactured and measured elements. This paper deals with an approach to have such elements available to build advanced types of packages in shorter time compared to classical approaches. The approach is a general approach but it is demonstrated with an advanced two-level package-on-package technology with a leading edge IC technology. It is also used explain the build-up of a construction kit of RF-blocks from the design phase of test structures up to measurement of such structures, qualification and model building. From the test structure more general structures can be derived and used in the design of future 5G applications. This enables better time-to-market, reduces cost and provides higher design validation in terms of first time right.