Uptake Rate of Hydrogen Getter for Effectively Removing Outgassed H2 from Microelectronic Packages

Hydrogen absorption kinetic properties of palladium foil-based getter elements have been studied by manometric method based pressure amplitude measurement. The getter H2 uptake rate can be simply converted by pressure amplitude change, and can be fairly described by a mixed gas sorption modeling analysis. It has been found that the sorption rate of Pd-based getter element has a maximum rate of 40 ppm/min at initial absorption stage but it gets slowly down to 0.5ppm/min when approaching maximum sorption capacity, determined by a getter foil thickness. Based on different H2 outgassing rates of metal and polymer based package materials, a safety factor based methodology has been proposed for down selecting an appropriate getter element that can effectively removing outgassed H2 from microelectronic packages.

High Heat Resistant Peelable Temporary Bonding Film and New Debonding System with Xe Flash Light Irradiation

We have developed a new temporary bonding film (TBF) and new debonding system with Xe flash light irradiation, named photonic release system, for advanced package assembly process. Since new TBF has a high Tg over 200 °C after curing and shows good chemical resistance to developer, resist stripper, and plating chemicals, no delamination, voiding, and swelling were observed after thermal and chemical treatment in the bonded structure of wafer and glass carrier. In addition, by adopting a metal-sputtered glass carrier, wafer could be debonded by Xe flash light irradiation in less than 1 ms through the glass carrier with no damage. Residual TBF on the wafer surface could be peeled off smoothly at ambient temperature without residue on the wafer. In this research, we also demonstrated the good applicability of this temporary bonding film to the typical packaging process by using test vehicle including 12 inch mold wafer and the advantage of photonic release system.

Control of Void Formation in Adhesively Bonded Joints in the Presence of Filler

Adhesively bonded joints are ubiquitous in electronic assemblies that are used in a wide range of applications, which include automotive, medical, military, space and communications. The steady drive to reduce the size of assemblies in all of these applications, while providing increased functionality, generates a need for adhesive joints of higher strength, improved thermal and electrical conductivity and better dielectric isolation. All of these attributes of adhesive joints are degraded by the presence of voids in them. The quest to minimize voids in bonded structures motivated a previous study of their formation in a solvent cast, die bond epoxy film, which undergoes a liquid phase transition during cure. That work is extended in this study by including the effects of various filler morphologies in the adhesive. Fillers are added to adhesives to facilitate handling of thin sheet formats, control bond line thickness and reduce coefficient of thermal expansion. As such, fillers are selected to be inert with respect to the adhesive chemistry, while being readily wetted by it in the liquid state. Common filler morphologies include woven and molded open meshes, fibers chopped to uniform length, and spheres of uniform or distributed diameters. Void formation is influenced by a number factors, which include wettability of the bonded surfaces, adsorbed water, amount of solvent retained in the film, volume of entrapped air, thermal profile of the cure schedule, and clamping pressure during cure. The presence of fillers in the adhesive adds the additional factors of constrained diffusion paths and increased area for void nucleation. We have changed our approach to modeling the diffusion of volatile species in adhesive joints from a finite difference calculation in a uniform adhesive medium used previously, to a finite element model of a complex diffusion space. The open source program Gmsh is used to generate the diffusion space from a set of input parameters. The calculations of concentration profiles and diffusion fluxes of volatile species at the void interface are made using the open source finite element program elmer. As done previously, the position of the void interface is updated by integrating the product of time and flux of diffusing species over the area of the interface. The internal pressure of the void is determined by application of the Young-Laplace equation, while Henry’s law is used to estimate the concentration of diffusing species adjacent to the void interface. The calculation proceeds for a time equivalent to the integral of the time temperature product required to achieve a 70% cure state of the adhesive, at which point the void interface is immobile. The experimental approach is the same as used previously, with the filled adhesive sandwiched between glass slides and cured on a hot plate while imaged through a microscope. Images are automatically captured and analyzed by using the open source program imageJ, which allows us to track the evolution of individual voids as well as the time dependent distribution of the void population. We are working to correlate these experimental results with the predictions of our finite element calculations to allow us to make insightful choices of adhesives and optimize our bonding processes.

Ultra-low Residue Flux Applications in RF Front-End Packages

With the leap into the 5G era, the demand for improvements in the performance of mobile phones is on the rise. This is also true for the quantity of radio frequency (RF) front-end integrated circuits (ICs), especially for RF switches and low noise amplifiers (LNA). It is well-known that improvements in performance depend on the combination of new design, package technology, and choice of materials. Ultra-low residue (ULR) flux is an innovative, truly no-clean, flip-chip bonding material. By using ULR flux, the typical water-wash cleaning process can be removed and, in some instances, package reliability can be improved as well. This simplified assembly process will help to reduce total packaging costs. This paper will discuss the application of ULR fluxes on land grid arrays (LGAs) and quad-flat no-leads/dual-flat no-leads (QFN/DFN) packages for RF front-end ICs, as well as the reflow process. The solder joint strength and reliability study will be shared as well.

Optimization of High-Speed Electrolytic Plating of Copper Pillar to Achieve a Flat Top Morphology and Height Uniformity

Cu plating bath for high-speed electrodeposition of Cu pillar was designed in consideration of a flat top morphology of pillar and a pillar height uniformity. An ideal polarization curve was assumed for the flat top morphology. To obtain the ideal polarization curve, an effect of organic additive concentration and solution agitation on the polarization curve were investigated. The basic bath components were optimized considering a Wagner number to improve pillar height uniformity. To confirm the pillar top morphology and the pillar height uniformity, a 300 mm diameter wafer was plated with Cu at 20 A/dm2. As a result, improved pillar top morphology and pillar height uniformity were obtained. The optimized plating bath was applied to the plating of large-size panel of 415 × 510 mm.

Optical Data Link Module for Data Transmission in Smart Catheters

We demonstrate a stand-alone optical data link module (ODLM) that fits in the limited space budget of smart imaging catheters. The module is based on an extension of the Flex-to-Rigid (F2R) technology platform for miniaturized system integration. The ODLM is a silicon-based interposer that comprises a commercially available Vertical Cavity Surface Emitting Laser (VCSEL), which has its electrical contacts and laser emitting spot on the same surface. With the flexible interconnects, the ODLM reroutes the flip-chipped VCSEL electrical contacts to the side that is perpendicular to the surface of the VCSEL. This enables the ODLM to be mounted on a flex-PCB and fit into the limited space in the distal tip of the smart catheter. An optical fiber that runs in parallel to the catheter shaft is inserted into the through-silicon hole (TSH) of the ODLM and self-aligned to the VCSEL for optical data transmission. The design of the ODLM and the F2R technology platform are introduced, and an ODLM demonstrator is fabricated and presented.

Plasma Surface Engineering: An Enabling Technology Designed to Clean and Protect Printed Circuit Boards

Long term reliability and performance of printed circuit boards (PCBs) are strongly affected by the presence of surface contaminants from the manufacturing and assembly processes. Flux and solder residue, dust particles, oils and greases are often found on the assembled boards and can inhibit the successful application of conformal coatings that are used to protect the electronic components. Surface contaminants can cause coating delamination, dendritic growth, electromigration, corrosion and result in compromised coatings. In the first part of this paper, the fundamental mechanism of plasma-induced removal of organic contaminants from PCBs will be presented. While vacuum based plasmas are considered the traditional solvent-free technology for surface cleaning, a new approach involving air plasma operating under atmospheric pressure conditions is gaining interest due to its adaptability for industrial inline processing. The low concentration of oxygen that is available in the plasma gas is effective in vaporizing organic contaminants leaving behind a clean surface. Additionally, atmospheric plasma processes focusing on the development of functional nanocoatings on PCBs have been investigated. These plasma-enhanced chemical vapor deposition (PECVD) processes involve the delivery and vaporization of small volumes of solvent-free precursors that react with the plasma to form thin coatings on polymer substrates. Depending on the chemical structure of the precursor used, adhesion promoting, water repellant or electrical barrier coatings of 30–100nm thickness can be deposited. These protective functional coatings do not require any curing or special handling and no chemical waste is generated. The latest developments in atmospheric pressure PECVD for electronics protection will be presented in the second part of the paper. Besides the improvement of device performance and reliability, the application of PECVD has the potential to replace chemical substances such as primers known to have harmful impact on human health and the environment.

Enhancement of ESD performances of Silicon Capacitors for RFID solutions

Radio-Frequency IDentification devices such as smart cards and RFID tags are based on the presence of a resonant tuned LC circuit associated to the RFID Integrated Circuit (IC). The use of discrete capacitor, external to the IC gives greater flexibility and design freedom. In the race of miniaturization, manufacturers of RFID devices always require smaller electronic components. To save space and in the same time improve performances, capacitors are exposed to height and volume constraints. In the same time, the capacitor has to withstand ESD stresses that can occur during the assembly of the device and during operation. Murata has developed a unique thin capacitor technology in silicon. This paper reports the development of a range of low profile capacitors with enhanced ESD performances. The manufacturing process optimization and the design adjustments will be presented here. The process was optimized by taking into account the main electrical parameters: leakage current, breakdown voltage, capacitance density, capacitance accuracy, Equivalent Series Resistance (ESR) and Self-Resonant Frequency (SRF). The dielectric stack was defined in order to integrate up to 330pF in 0402 case. The process architecture, based on accurate planar capacitor with thick dielectric will be discussed. With this architecture there is no constraint to reach low thickness, such as 100μm or even lower. The ESD threshold of each Silicon Capacitor was investigated with design variations associated to Human Body Model measurements. A Single Project Wafer (SPW) was founded with 36 different capacitor designs. Design modulations specifically addressed the orientation and position of the contacts openings. Special care was taken to maximize the width of the contact holes and metal tracks. A mosaic approach, constructed out of a massive network of parallelized elementary cells was also implemented, so that the charges of the ESD pulse do not concentrate at the same place, leading to electrical failure. Examples of defects due to ESD stress will be shown with failure analysis cross-sections and ways to enhance the ESD threshold by design will be illustrated.

Reliability Simulation of Cu/Polymer interface in Fan-out Wafer Level Packaging

In order to improve the performance and reliability of the package, the interlayer dielectric (Polymer) must not be delaminated and materials should not fracture due to thermal stresses during the operation or the manufacturing process. If the reliability of the package can be known in advance by simulation, it can be expected to greatly help in material selection and package design. Firstly, we created material-specific master curves (time–temperature superposition) by considering the measurement results of the Peel Test at the Cu/Polymer interface and the mechanical properties of polymer. The critical Energy Release Rate (𝒢𝒸) could be calculated by its master curve. Secondary, we calculated the Energy Release Rate (𝒢) from Finite Element Analysis (FEA) in the package model structure. Finally, delamination is judged by normalizing 𝒢/𝒢𝒸. This study has made it possible to simulate the delamination possibility of Cu/Polymer interface at arbitrary temperatures and displacement rates from basic material data and FEA analysis of the package model structure.

Acceleration Factors and Life Predictions

Acceleration factors (AF) are key to designing an effective accelerated life test (ALT). They represent the ratio of the time in field to the time in test for a particular event to occur (typically a failure event related to a specific failure mechanism). Time to failure for a device generally correlates with the amount of stress applied (the higher the stress, the quicker the device will fail), and failure models exist to mathematically define that correlation for various failure mechanisms. This allows for use of a higher stress in test than in the field, thereby providing an acceleration factor that shortens the time in test to demonstrate a failure-free time period. ALT can take the form of qualitative or quantitative testing. The latter is used to determine the life characteristics of the device with some reliability and confidence level. Usage rate acceleration and higher stress acceleration can be used. It is important to consider the design limits of the device based on its specification and material properties, and limit the stress levels in test so as not to induce failure mechanisms that the device would not otherwise have experienced in the field. ALT results are used to make life predictions for the device tested. With no failures, the test results demonstrate the required reliability and confidence level metrics for the failure mechanism of interest. With several failures, a reliability software tool can be used with the appropriate analysis method, rank method, and confidence bounds method chosen in order to extrapolate to an expected life in test. The equivalent field life is based on multiplying the expected life in test by the AF. If the field stress and/or test stress are not constant, there are multiple acceleration factors to utilize. As a result, an equivalent acceleration factor needs to be calculated and used as the AF when predicting equivalent field life.