Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis

2016 ◽

Author(s):

Kuen-Wey Lin ◽

Yih-Lang Li ◽

Rung-Bin Lin

Keyword(s):

Standard Cell ◽

Layout Synthesis

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CELLERITY: A Fully Automatic Layout Synthesis System For Standard Cell Libraries

Proceedings of the 34th Design Automation Conference ◽

10.1109/dac.1997.597167 ◽

2005 ◽

Cited By ~ 12

Author(s):

M. Guruswamy ◽

R.L. Maziasz ◽

D. Dulitz ◽

S. Raman ◽

V. Chiluvuri ◽

...

Keyword(s):

Standard Cell ◽

Synthesis System ◽

Layout Synthesis ◽

Automatic Layout ◽

Fully Automatic

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Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families

2019 IEEE International Superconductive Electronics Conference (ISEC) ◽

10.1109/isec46533.2019.8990962 ◽

2019 ◽

Author(s):

Lieze Schindler ◽

Ruben van Staden ◽

Coenrad J. Fourie ◽

Christopher L. Ayala ◽

Johannes A. Coetzee ◽

...

Keyword(s):

Standard Cell ◽

Layout Synthesis ◽

Placement And Routing

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Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis

10.1109/iccd53106.2021.00085 ◽

2021 ◽

Author(s):

Kyeongrok Jo ◽

Taewhan Kim

Keyword(s):

Standard Cell ◽

Layout Synthesis

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Standard-Cell, Open-Architecture Power Conversion Systems

10.21236/ada468619 ◽

2005 ◽

Author(s):

D. Boroyevich ◽

F. Wang ◽

F. C. Lee ◽

W. G. Odendaal ◽

S. Edwards

Keyword(s):

Power Conversion ◽

Open Architecture ◽

Standard Cell

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Power and Variation Improved Near-Vt Standard Cell Library for 28-nm FDSOI

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s46989.2019.9320687 ◽

2019 ◽

Author(s):

Wing-Tsi Wong ◽

Kamlesh Singh ◽

Jos Huisken ◽

Jose Pineda de Gyvez

Keyword(s):

Standard Cell ◽

Standard Cell Library ◽

Cell Library ◽

28 Nm

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Optimal layout synthesis for quantum computing

Proceedings of the 39th International Conference on Computer-Aided Design ◽

10.1145/3400302.3415620 ◽

2020 ◽

Author(s):

Bochen Tan ◽

Jason Cong

Keyword(s):

Quantum Computing ◽

Optimal Layout ◽

Layout Synthesis

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24.4 A 5nm [email protected] and [email protected] 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9366000 ◽

2021 ◽

Author(s):

Hidehiro Fujiwara ◽

Yi-Hsin Nien ◽

Chih-Yu Lin ◽

Hsien-Yu Pan ◽

Hao-Wen Hsu ◽

...

Keyword(s):

Standard Cell ◽

Register File

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A 15000 Tuning Range Scalable Feed-Forward Oscillator With 0.05mm2 Area in CMOS Standard-Cell Format

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401776 ◽

2021 ◽

Author(s):

Julian Arenas ◽

Juan Sebastian Moya ◽

Elkim Roa

Keyword(s):

Tuning Range ◽

Standard Cell ◽

Feed Forward

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Interactive and Scalable Layout Synthesis with Design Templates

2020 IEEE International Conference on Artificial Intelligence and Virtual Reality (AIVR) ◽

10.1109/aivr50618.2020.00049 ◽

2020 ◽

Author(s):

Hameedullah Farooki ◽

Esra Ataer-Cansizoglu ◽

Jae-Woo Choi ◽

Tomer Weiss

Keyword(s):

Layout Synthesis

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Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis

Multiple-patterning lithography-aware routing for standard cell layout synthesis

CELLERITY: A Fully Automatic Layout Synthesis System For Standard Cell Libraries

Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families

Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis

Standard-Cell, Open-Architecture Power Conversion Systems

Power and Variation Improved Near-Vt Standard Cell Library for 28-nm FDSOI

Optimal layout synthesis for quantum computing

24.4 A 5nm [email protected] and [email protected] 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

A 15000 Tuning Range Scalable Feed-Forward Oscillator With 0.05mm2 Area in CMOS Standard-Cell Format

Interactive and Scalable Layout Synthesis with Design Templates

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