Design and Implementation of Memory BIST for Hybrid Cache Architecture

2021 6th International Conference on Communication and Electronics Systems (ICCES) ◽

10.1109/icces51350.2021.9489225 ◽

2021 ◽

Author(s):

Suraj B Ghale ◽

Namita P

Keyword(s):

Design And Implementation ◽

Cache Architecture ◽

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Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture

The Computer Journal ◽

10.1093/comjnl/bxv103 ◽

2015 ◽

Vol 59 (5) ◽

pp. 685-700

Author(s):

Ju-Hee Choi ◽

Gi-Ho Park

Keyword(s):

Capacity Management ◽

Management Policy ◽

Cache Architecture ◽

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A low-power phase change memory based hybrid cache architecture

Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08 ◽

10.1145/1366110.1366204 ◽

2008 ◽

Author(s):

Prasanth Mangalagiri ◽

Karthik Sarpatwari ◽

Aditya Yanamandra ◽

VijayKrishnan Narayanan ◽

Yuan Xie ◽

...

Keyword(s):

Low Power ◽

Phase Change ◽

Phase Change Memory ◽

Cache Architecture ◽

Hybrid Cache ◽

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A hybrid cache architecture of shared memory and meta-table used in big multimedia query

2016 IEEE/ACIS 15th International Conference on Computer and Information Science (ICIS) ◽

10.1109/icis.2016.7550809 ◽

2016 ◽

Author(s):

Yun-Te Lin ◽

Yi-Hao Hsiao ◽

Fang-Pang Lin ◽

Chung-Ming Wang

Keyword(s):

Shared Memory ◽

Cache Architecture ◽

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Low power data-aware STT-RAM based hybrid cache architecture

2016 17th International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2016.7479181 ◽

2016 ◽

Author(s):

Mohsen Imani ◽

Shruti Patil ◽

Tajana Rosing

Keyword(s):

Low Power ◽

Cache Architecture ◽

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Adaptive replacement policy for hybrid cache architecture

IEICE Electronics Express ◽

10.1587/elex.11.20140946 ◽

2014 ◽

Vol 11 (22) ◽

pp. 20140946-20140946 ◽

Author(s):

Ju-Hee Choi ◽

Gi-Ho Park

Keyword(s):

Replacement Policy ◽

Cache Architecture ◽

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3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2011.6026484 ◽

2011 ◽

Author(s):

Koji Inoue ◽

Shinya Hashiguchi ◽

Shinya Ueno ◽

Naoto Fukumoto ◽

Kazuaki Murakami

Keyword(s):

Power Consumption ◽

Low Power ◽

High Performance ◽

Low Power Consumption ◽

Cache Architecture ◽

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Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture

2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) ◽

10.1109/coolchips49199.2020.9097643 ◽

2020 ◽

Author(s):

Masayuki Sato ◽

Xue Hao ◽

Kazuhiko Komatsu ◽

Hiroaki Kobayashi

Keyword(s):

Energy Efficient ◽

Efficient Design ◽

Cache Architecture ◽

Hybrid Cache ◽

Energy Efficient Design

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Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES '16 ◽

10.1145/2968456.2968477 ◽

2016 ◽

Author(s):

Mimi Xie ◽

Mengying Zhao ◽

Chen Pan ◽

Hehe Li ◽

Yongpan Liu ◽

...

Keyword(s):

Energy Harvesting ◽

Cache Architecture ◽

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Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

IEEE Transactions on Computers ◽

10.1109/tc.2015.2435772 ◽

2016 ◽

Vol 65 (3) ◽

pp. 940-951 ◽

Author(s):

Junwhan Ahn ◽

Sungjoo Yoo ◽

Kiyoung Choi

Keyword(s):

Energy Efficient ◽

Cache Architecture ◽

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Hybrid cache architecture with disparate memory technologies

Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09 ◽

10.1145/1555754.1555761 ◽

2009 ◽

Author(s):

Xiaoxia Wu ◽

Jian Li ◽

Lixin Zhang ◽

Evan Speight ◽

Ram Rajamony ◽

...

Keyword(s):

Cache Architecture ◽

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