A formal approach for modeling and verification of bus bridge based on Petri Net and model checking

Author(s):  
Guoyin Zhang ◽  
Ming Liu ◽  
Aihong Yao
2017 ◽  
Vol 2017 ◽  
pp. 1-10 ◽  
Author(s):  
Long Zhang ◽  
Wenyan Hu ◽  
Wanxia Qu ◽  
Yang Guo ◽  
Sikun Li

Mobile cyber-physical systems (CPSs) are very hard to verify, because of asynchronous communication and the arbitrary number of components. Verification via model checking typically becomes impracticable due to the state space explosion caused by the system parameters and concurrency. In this paper, we propose a formal approach to verify the safety properties of parameterized protocols in mobile CPS. By using counter abstraction, the protocol is modeled as a Petri net. Then, a novel algorithm, which uses IC3 (the state-of-the-art model checking algorithm) as the back-end engine, is presented to verify the Petri net model. The experimental results show that our new approach can greatly scale the verification capabilities compared favorably against several recently published approaches. In addition to solving the instances fast, our method is significant for its lower memory consumption.


2006 ◽  
Vol 11 (5) ◽  
pp. 1297-1301 ◽  
Author(s):  
Zhou Conghua ◽  
Chen Zhenyu

2011 ◽  
Vol 113 (3-4) ◽  
pp. 229-264 ◽  
Author(s):  
Steve Hostettler ◽  
Alexis Marechal ◽  
Alban Linard ◽  
Matteo Risoldi ◽  
Didier Buchs
Keyword(s):  

Author(s):  
Vanessa Grosch

Requirements traceability enables the linkage between all development artifacts during the development process. Within model-based testing, requirements traceability links the original requirements with test model elements and generated test cases. Current approaches are either not practical or lack the necessary formal foundation for generating requirements-based test cases using model-checking techniques involving the requirements trace. This paper describes a practical and formal approach to ensure requirements traceability. The descriptions of the requirements are defined on path fragments of timed automata or timed state charts. The graphical representation of these paths is called a computation sequence chart (CSC). CSCs are automatically transformed into temporal logic formulae. A model-checking algorithm considers these formulae when generating test cases.


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