Low power multiplier using algorithmic noise tolerant architecture

2016 ◽  
Author(s):  
S. Fathima ◽  
S. Uma
Keyword(s):  
Low Power ◽  
Noise Tolerant ◽  
Low Power Multiplier

scholarly journals A Low Power Multiplier using a 24-Transistor Latch Adder

2015 ◽  
Vol 8 (19) ◽  
Author(s):  
Savio Victor Gomes ◽  
P. Sasipriya ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
Low Power Multiplier

Driving-Noise-Tolerant Broadband Polymer/Silica Hybrid Thermo-Optic Switch with Low Power Consumption

2012 ◽  
Vol 31 (5) ◽  
pp. 299-315 ◽  
Author(s):  
Lei Liang ◽  
Chuan-Tao Zheng ◽  
Xiao-Qiang Sun ◽  
Fei Wang ◽  
Chun-Sheng Ma ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Noise Tolerant ◽  
Silica Hybrid

A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique

2011 ◽  
Author(s):  
Manisha Pattanaik ◽  
Shashank Parashar ◽  
Chaudhry Indra Kumar ◽  
Akanksha Chouhan ◽  
Vikas Mahor
Keyword(s):  
Low Power ◽  
High Performance ◽  
Logic Design ◽  
Design Technique ◽  
Power Noise ◽  
Noise Tolerant

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

2002 ◽  
Vol 10 (4) ◽  
pp. 469-476 ◽  
Author(s):  
A. Solomatnikov ◽  
D. Somasekhar ◽  
N. Sirisantana ◽  
K. Roy
Keyword(s):  
Low Power ◽  
High Performance ◽  
Noise Tolerant ◽  
Circuit Family
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