Low Power Arithmetic Circuit Design for Multimedia Applications

The objective of this chapter is to describe the various designed arithmetic circuit for an application of multimedia circuit that can be used in a high-performance or mobile microprocessor with a particular set of optimisation criteria. The aim of this chapter is to describe the design method of binary arithmetic especially using by CMOS and Pass Transistor Logic technique. The pass transistor techniques are reduced the noise margin for small circuit, which can be explained in this chapter. This chapter further describe the types of arithmetic and its techniques. The technique design principle procedure should make the following decisions: circuit family (complementary static CMOS, pass-transistor, or Shannon Theorem based); type of arithmetic to be used. The decisions on the designed logic level significantly affect the propagation delay, area and power dissipation.

Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits

Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, Cload, temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3 V which can be used for different transistor size up to 36 μm. Average power dissipation is 0.2 μW at 1 V and 30 μW at 2 V at 100 ff Cload 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58 μW. Modified PFAL circuit reduces average power by 9% approximately.

AN UNIVERSAL PHENOMENON IN MUTUALLY COUPLED CHUA'S CIRCUIT FAMILY

This paper presents the universality of the coexistence of complete synchronization with the recently new proposed inverse π-lag synchronization, in the case of mutually coupled systems of Chua's circuit family. The phenomenon of multistability and the nature of this circuit family systems are the key-points which lead to the explanation of this coexistence. For the need of this work, the most representative circuit of this circuits' family, the Chua oscillator, is used. Simulation results confirm this universality in the class of Chua's circuit family.

BISTABILITY AND HYSTERESIS IN SYMMETRIC 3D PIECEWISE LINEAR OSCILLATORS WITH THREE ZONES

A degeneration in a two-parameter setting for the focus-center-limit cycle bifurcation of symmetric 3D piecewise linear systems with three zones is studied. The analysis gives a rigorous mathematical explanation for the appearance in piecewise linear oscillators of up to two limit cycles along with a related hysteresis phenomenon. A piecewise linear oscillator, which is a member of the generic Chua's circuit family, is shown to exhibit bistability, that is, coexistence of stable oscillations with a stable steady state. Also, the corresponding hysteresis in the appearance of periodic oscillations is explained. The analytical results included in the paper predict accurately the observed behavior.

Quantum lower bounds for fanout

We consider the resource bounded quantum circuit model with circuits restricted by the number of qubits they act upon and by their depth. Focusing on natural universal sets of gates which are familiar from classical circuit theory, several new lower bounds for constant depth quantum circuits are proved. The main result is that parity (and hence fanout) requires log depth quantum circuits, when the circuits are composed of single qubit and arbitrary size Toffoli gates, and when they use only constantly many ancill\ae. Under this constraint, this bound is close to optimal. In the case of a non-constant number $a$ of ancill\ae\ and $n$ input qubits, we give a tradeoff between $a$ and the required depth, that results in a non-constant lower bound for fanout when $a = n^{1-o(1)}$. We also show that, regardless of the number of ancill\ae\, arbitrary arity Toffoli gates cannot be simulated exactly by a constant depth circuit family with gates of bounded arity.