A Bit Flipping Viterbi Decoding Algorithm Based on CRC Check for Convolutional Code

In this paper, we use MATLAB software to build the physical layer transceiver of the Digital Video Broadcasting Terrestrial System (DVB-T) and Additive White Gaussian Noise (AWGN) is added into the transmitted signal during its transmission. The transmitted signal passes through modulation, demodulation, encoding and decoding processes the resulting demodulated signal is compared with the transmitted signal to calculate its Bit Error Rate (BER). Three modulation formats, QPAK, 16-QAM and 64-QAM are simulated and through various Signal to Noise (SNR) ratio to evaluate the system performance. Various encoding techniques such as Reed Solomon Code, Convolutional Code and Viterbi Decoding [1-6] have been implemented and through simulation to make detailed system performance analysis and comparison. detailed system performance simulation, analysis and comparisons.

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Error Performance Analysis of the K-best Viterbi Decoding Algorithm

2018 International Symposium on Information Theory and Its Applications (ISITA) ◽

10.23919/isita.2018.8664365 ◽

2018 ◽

Author(s):

Hideki Yoshikawa

Keyword(s):

Performance Analysis ◽

Viterbi Decoding ◽

Decoding Algorithm ◽

Error Performance

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The Viterbi Decoding Scheme for FPGA

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.63-64.835 ◽

2011 ◽

Vol 63-64 ◽

pp. 835-840

Author(s):

Ke Han ◽

Zhong Liang Deng ◽

Lian Ming Xu

Keyword(s):

Power Consumption ◽

Mobile Communication ◽

Communication System ◽

Viterbi Algorithm ◽

Convolutional Code ◽

Fpga Implementation ◽

Viterbi Decoding ◽

Mobile Communication System ◽

Uniform State ◽

Branch Weight

This paper analyzes the principle of Viterbi algorithm which can be used in the norm of the mobile communication system. Then a new Viterbi decoding scheme of (2, 1, 7) convolutional code is presented for FPGA implementation. To take advantage of the FPGA, a new branch weight algorithm and uniform state weight memories is used. At last, a new decoding circuit which can work on 35MHz and can achieve 120 kbs in decoding speed was designed. To use the design of survival path exchange register module, it can decrease the power consumption and the RAM size.

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