Implementation of the one dimensional discrete cosine transform using the residue number system

In this paper, multifunction residue number system (RNS) modulo (2n ± 1) multipliers are proposed. By adopting common circuits for summing up the partial products with extra controls, our proposed multipliers could perform both modulo (2n + 1) and (2n - 1) multiplications. The levels for summation of partial products are n + 1, which are same as the conventional modulo multipliers which with only one kind of modulo multiplications. The proposed multifunction modulo (2n ± 1) multipliers can save at least about 42.5% area under the same delay constraints and above 65.8% Area × Delay Product (ADP) compared with the one composed of modulo (2n + 1) and modulo (2n - 1) multiplication operations. Our proposed multipliers could be applied to ease the tremendous computation overload in the real-time processing applications.

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RSA decryption using the one-hot residue number system

Proceedings of the 39th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1996.594238 ◽

2002 ◽

Author(s):

W.A. Chren ◽

C.H. Brogdon

Keyword(s):

Number System ◽

Residue Number System ◽

Residue Number ◽

The One

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An improved hardware implementation of the one hot Residue Number System

2014 Fifth Argentine Symposium and Conference on Embedded Systems SASE/CASE 2014 ◽

10.1109/sase-case.2014.6914463 ◽

2014 ◽

Author(s):

Carlos Arturo Gayoso ◽

Claudio Gonzalez ◽

Leonardo Arnone ◽

Miguel Rabini ◽

Jorge Castineira Moreira

Keyword(s):

Hardware Implementation ◽

Number System ◽

Residue Number System ◽

Residue Number ◽

The One

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Binary to RNS encoder for the moduli set {2n-1, 2n, 2n+1} with embedded diminished-1 channel for DSP application

Facta universitatis - series Electronics and Energetics ◽

10.2298/fuee1601101k ◽

2016 ◽

Vol 29 (1) ◽

pp. 101-112

Author(s):

Ivan Krstic ◽

Negovan Stamenkovic ◽

Vidosav Stojanovic

Keyword(s):

Dynamic Range ◽

Digital Signal ◽

Number System ◽

Residue Number System ◽

The Other ◽

Minimal Amount ◽

Residue Number ◽

Fpga Chip ◽

The One ◽

Xilinx Fpga

A binary-to-residues encoder (forward encoder) is an essential building block for the residue number system digital signal processing (RNS DSP) and as such it should be built with a minimal amount of hardware and be efficient in terms of speed and power. The main parts of the forward encoder are residue generators which are usually classified into two categories: the one based on arbitrary moduli-set which make use of look-up tables, and the other based on the special moduli sets. A new memory less architecture of binary-to-RNS encoder based on the special moduli set {2n?1,2n,2n+1} with embedded modulo 2n+1 channel in the diminished-1 representation is presented. Any of two channels (standard modulo 2n +1, or modulo 2n+1 in the diminished-1 representation) operation can be performed by using a single switch. The proposed encoder has been implemented on a Xilinx FPGA chip for the various dynamic range requirements.

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A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation

Journal of Circuits System and Computers ◽

10.1142/s0218126603000878 ◽

2003 ◽

Vol 12 (01) ◽

pp. 111-123 ◽

Cited By ~ 1

Author(s):

Javier Ramírez ◽

Antonio García

Keyword(s):

Digital Signal ◽

Number System ◽

Residue Number System ◽

Quadratic Residue ◽

Programmable Logic ◽

Cosine Transform ◽

Speed Increase ◽

Residue Number ◽

Field Programmable ◽

Field Programmable Logic

This paper assesses the arithmetic benefits provided by the Residue Number System (RNS) for building Digital Signal Processing (DSP) systems with Field-Programmable Logic (FPL) technology. The quantifiable benefits of this approach are studied in the context of a new Fast Cosine Transform (FCT) architecture enhanced by using the Quadratic Residue Number System (QRNS). The system reduces the number of adders and multipliers required for the N-point Discrete Cosine Transform (DCT) and provides high throughput. For an FPL-based implementation, the proposed design gets significant improvements over an equivalent 2C structure. By using up to 6-bit moduli, an overall increase in the system performance of about 140% is achieved. If this speed increase is considered along with the penalty in device resources, the presented QRNS-based FCT system provides an improvement in the area-delay figure factor of about 20%. Finally, the conversion overhead was carefully studied and it was found that the quantifiable benefits of the proposed design are not affected when converters are included.

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