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Low-power High-throughput Deblocking Filter Architecture for H.264/AVC
2009 International Conference on Electronic Computer Technology
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10.1109/icect.2009.109
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2009
◽
Cited By ~ 7
Author(s):
NamThang Ta
◽
JinSeon Youn
◽
HuiGon Kim
◽
JunRim Choi
◽
Seung-Soo Han
Keyword(s):
Low Power
◽
High Throughput
◽
Deblocking Filter
◽
Filter Architecture
Download Full-text
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References
A low-power deblocking filter architecture for H.264 advanced video coding
2007 IFIP International Conference on Very Large Scale Integration
◽
10.1109/vlsisoc.2007.4402496
◽
2007
◽
Cited By ~ 1
Author(s):
Jaemoon Kim
◽
Sangkown Na
◽
Chong-Min Kyung
Keyword(s):
Low Power
◽
Video Coding
◽
Deblocking Filter
◽
Filter Architecture
◽
Advanced Video Coding
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Low-power, high-throughput deblocking filter for H.264/AVC
2010 International Symposium on System on Chip
◽
10.1109/issoc.2010.5625535
◽
2010
◽
Cited By ~ 1
Author(s):
Muhammad Nadeem
◽
Stephan Wong
◽
Georgi Kuzmanov
◽
Ahsan Shabbir
◽
Muhammad Faisal Nadeem
◽
...
Keyword(s):
Low Power
◽
High Throughput
◽
Deblocking Filter
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A high-throughput low-power hardware architecture for H.264 deblocking filter
2010 2nd International Conference on Computer Engineering and Technology
◽
10.1109/iccet.2010.5485615
◽
2010
◽
Cited By ~ 2
Author(s):
Xiaoliang Chen
◽
Weiyi Xia
◽
Xiaofeng Lu
Keyword(s):
Low Power
◽
High Throughput
◽
Hardware Architecture
◽
Deblocking Filter
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High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems
IEEE Access
◽
10.1109/access.2019.2930149
◽
2019
◽
Vol 7
◽
pp. 99642-99650
◽
Cited By ~ 1
Author(s):
Prayline Rajabai C.
◽
S. Sivanantham
Keyword(s):
Video Coding
◽
High Throughput
◽
Deblocking Filter
◽
Parallel Edge
◽
Coding Systems
◽
Edge Filter
◽
Filter Architecture
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An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.
◽
10.1109/aspdac.2005.1466238
◽
2005
◽
Cited By ~ 6
Author(s):
Lingfeng Li
◽
S. Goto
◽
T. Ikenaga
Keyword(s):
Deblocking Filter
◽
Parallel Memory
◽
Filter Architecture
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A high throughput deblocking filter design supporting multiple video coding standards
2009 IEEE International Symposium on Circuits and Systems
◽
10.1109/iscas.2009.5118278
◽
2009
◽
Cited By ~ 6
Author(s):
Cheng-An Chien
◽
Hsiu-Cheng Chang
◽
Jiun-In Guo
Keyword(s):
Video Coding
◽
High Throughput
◽
Filter Design
◽
Deblocking Filter
◽
Coding Standards
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Design A Low Power and High Throughput 130nm Full Adder Utilising Exclusive-OR And Exclusive- NOR Gates
Journal of VLSI Circuits and Systems
◽
10.31838/jvcs/03.02.05
◽
2021
◽
Vol 3
(2)
◽
Keyword(s):
Low Power
◽
High Throughput
◽
Full Adder
◽
Exclusive Or
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A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process
2016 International Conference on IC Design and Technology (ICICDT)
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10.1109/icicdt.2016.7542042
◽
2016
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Author(s):
Xuan-Thuan Nguyen
◽
Hong-Thu Nguyen
◽
Cong-Kha Pham
Keyword(s):
Low Power
◽
High Throughput
◽
Low Power Design
◽
Cmos Process
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High Throughput FIR Filter Architecture Using Retiming and Fine-Grain Pipelining
Advances in Intelligent Systems and Computing - Proceedings of International Conference on Intelligent Computing, Information and Control Systems
◽
10.1007/978-981-15-8443-5_71
◽
2021
◽
pp. 835-844
Author(s):
K. P. Heena
Keyword(s):
High Throughput
◽
Fir Filter
◽
Fine Grain
◽
Filter Architecture
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Design and Implementation of Low-Power High-throughput PRNGs for Security Applications
2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
◽
10.1109/vlsid.2019.00123
◽
2019
◽
Author(s):
Bikram Paul
◽
Apratim Khobragade
◽
Soumith Javvaji Sai
◽
Sushree Sila P. Goswami
◽
Sunil Dutt
◽
...
Keyword(s):
Low Power
◽
High Throughput
◽
Security Applications
◽
Design And Implementation
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