A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process

2016 ◽  
Author(s):  
Xuan-Thuan Nguyen ◽  
Hong-Thu Nguyen ◽  
Cong-Kha Pham
Keyword(s):  
Low Power ◽  
High Throughput ◽  
Low Power Design ◽  
Cmos Process

scholarly journals An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1760
Author(s):  
Folla Kamdem Jérôme ◽  
Wembe Tafo Evariste ◽  
Essimbi Zobo Bernard ◽  
Maria Liz Crespo ◽  
Andres Cicuttin ◽  
...  
Keyword(s):  
Low Power ◽  
High Throughput ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
High Luminosity ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Ultra Low Power ◽  
Front End

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

A 20-mV Input DC/DC Converter for Energy Harvesting Applications

2015 ◽  
Vol 24 (05) ◽  
pp. 1550070 ◽  
Author(s):  
Zheng Yang ◽  
Jingmin Wang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Power Management ◽  
High Efficiency ◽  
Low Power Design ◽  
Input Voltage ◽  
Voltage Source ◽  
Storage Capacitor ◽  
Cmos Process ◽  
Low Input

A low input step-up DC/DC converter and power manager in 0.18-μm CMOS process is presented. The proposed converter can work with the input voltage as low as 20 mV. The extremely low input voltage makes it suitable for energy harvesting and power management. Four logic controlled outputs provide the best voltage for various applications to accommodate low power design requirements. A low current low dropout regulator (LDO) is utilized to provide a regulated 2.2 V output for powering low power processors or other low power integrated circuit (ICs). Reserve energy on the storage capacitor CSTORE provides power when the input voltage source is unavailable, thus prolongs the life of the system and expands the application range. Extremely low quiescent current (6 μA) and high efficiency design (64%@300 μA load current) ensure the fastest possible charge times of the output reservoir capacitor. This work provides a complete power management solution for wireless sensing and data acquisition.

An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC

2014 ◽  
Vol 598 ◽  
pp. 365-370
Author(s):  
Shuo Zhang ◽  
Zong Min Wang ◽  
Liang Zhou
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Cmos Process ◽  
Total Current ◽  
Flash Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Offset

This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total current consumption of the primary one is -5.649mV with σ = 14.254mV and 57.18μA respectively.

Power mad [low-power design]

2004 ◽  
Vol 18 (3) ◽  
pp. 37
Author(s):  
J. Frenkil
Keyword(s):  
Low Power ◽  
Low Power Design

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

Low-Power Digital Part Design for a LF RFID tag in a Double-Poly 180 nm CMOS Process

2021 ◽  
Author(s):  
Kirill D. Liubavin ◽  
Igor V. Ermakov ◽  
Alexander Y. Losevskoy ◽  
Andrey V. Nuykin ◽  
Alexander S. Strakhov
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Rfid Tag ◽  
Digital Part

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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