FPGA Based Hardware Accelerator Design for Convolution Process in Convolutional Neural Network

Author(s):  
Ardian Dwi C ◽  
Trio Adiono ◽  
Nana Sutisna
2021 ◽  
Vol 16 (2) ◽  
pp. 1-10
Author(s):  
Kenshu Seto

In this paper, we present a brief survey on the system-level optimizations used for convolutional neural network (CNN) inference accelerators. For the nested loop of convolutional (CONV) layers, we discuss the effects of loop optimizations such as loop interchange, tiling, unrolling and fusion on CNN accelerators. We also explain memory optimizations that are effective with the loop optimizations. In addition, we discuss streaming architectures and single computation engine architectures that are commonly used in CNN accelerators. Optimizations for CNN models are briefly explained, followed by the recent trends and future directions of the CNN accelerator design.


2021 ◽  
Author(s):  
Ahmed J. Abd El-Maksoud ◽  
Abdallah Mohamed ◽  
Ahmed Tarek ◽  
Amr Adel ◽  
Amr Eid ◽  
...  

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