A serial-input serial-output encoder based on pipelined type I rotate-left-accumulator (RLA) circuit is presented for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Digital Terrestrial Multimedia Broadcasting (DTMB) standard. This encoding scheme can reduce the power consumption and save memory resource. FPGA implementation and simulation results show that the design meets the requirement of DTMB standard and simplifies the structure of the memory.
FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes
