Research on Double-Layer Networks-on-Chip for Inter-Chiplet Data Switching on Active Interposers

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

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Double-layer graphene on photonic crystal waveguide electro-absorption modulator with 12 GHz bandwidth

Nanophotonics ◽

10.1515/nanoph-2019-0381 ◽

2019 ◽

Vol 9 (8) ◽

pp. 2377-2385 ◽

Cited By ~ 4

Author(s):

Zhao Cheng ◽

Xiaolong Zhu ◽

Michael Galili ◽

Lars Hagedorn Frandsen ◽

Hao Hu ◽

...

Keyword(s):

Photonic Crystal ◽

Double Layer ◽

Slow Light ◽

Modulation Depth ◽

Photonic Crystal Waveguide ◽

Optical Modulators ◽

Layer Graphene ◽

Silicon Photonic ◽

On Chip ◽

Silicon Based

AbstractGraphene has been widely used in silicon-based optical modulators for its ultra-broadband light absorption and ultrafast optoelectronic response. By incorporating graphene and slow-light silicon photonic crystal waveguide (PhCW), here we propose and experimentally demonstrate a unique double-layer graphene electro-absorption modulator in telecommunication applications. The modulator exhibits a modulation depth of 0.5 dB/μm with a bandwidth of 13.6 GHz, while graphene coverage length is only 1.2 μm in simulations. We also fabricated the graphene modulator on silicon platform, and the device achieved a modulation bandwidth at 12 GHz. The proposed graphene-PhCW modulator may have potentials in the applications of on-chip interconnections.

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Deadlock-Free Adaptive Routing in Networks -on-Chip Using Overlapping Virtual Networks

IEEE Transactions on Computers ◽

10.1109/tc.2021.3067320 ◽

2021 ◽

pp. 1-1

Author(s):

Dong Xiang ◽

Xiang Ji ◽

Yuan Cai ◽

Binzhang Fu

Keyword(s):

Adaptive Routing ◽

Virtual Networks ◽

Networks On Chip ◽

On Chip

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Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽

10.3390/mi12010054 ◽

2021 ◽

Vol 12 (1) ◽

pp. 54

Author(s):

Yan-Li Zheng ◽

Ting-Ting Song ◽

Jun-Xiong Chai ◽

Xiao-Ping Yang ◽

Meng-Meng Yu ◽

...

Keyword(s):

Power Consumption ◽

Power Control ◽

Optical Networks ◽

Output Power ◽

Network Performance ◽

Transmission Loss ◽

Adaptive Routing ◽

Dijkstra Algorithm ◽

Networks On Chip ◽

On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

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Predicting Networks-on-Chip traffic congestion with Spiking Neural Networks

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2021.03.013 ◽

2021 ◽

Author(s):

Aqib Javed ◽

Jim Harkin ◽

Liam McDaid ◽

Junxiu Liu

Keyword(s):

Neural Networks ◽

Traffic Congestion ◽

Spiking Neural Networks ◽

Networks On Chip ◽

On Chip

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A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽

10.3390/mi12020183 ◽

2021 ◽

Vol 12 (2) ◽

pp. 183

Author(s):

Jose Ricardo Gomez-Rodriguez ◽

Remberto Sandoval-Arechiga ◽

Salvador Ibarra-Delgado ◽

Viktor Ivan Rodriguez-Abdala ◽

Jose Luis Vazquez-Avila ◽

...

Keyword(s):

Single Chip ◽

Synthesis Time ◽

Networks On Chip ◽

Data Dependencies ◽

Layered Architecture ◽

Systems On Chip ◽

Challenges And Opportunities ◽

Computing Platforms ◽

On Chip ◽

Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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