A design of analog front-end for passive UHF RFID tag

Author(s):  
Smail Hassouni ◽  
Hassan Qjidaa
Author(s):  
Shaojie Zhang ◽  
Lingling Sun ◽  
Hui Hong ◽  
Jun Liu ◽  
Jian Han ◽  
...  

Author(s):  
Zejun Wu ◽  
Jinfeng Huang ◽  
Jinpeng Shen ◽  
Xiaoxing Feng ◽  
Xin'an Wang

2015 ◽  
Vol 2015 ◽  
pp. 1-11 ◽  
Author(s):  
Shugo Mikami ◽  
Dai Watanabe ◽  
Yang Li ◽  
Kazuo Sakiyama

Passive radio-frequency identification (RFID) tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function.


2021 ◽  
Vol 2065 (1) ◽  
pp. 012007
Author(s):  
Qinglong Li ◽  
Yong Xu ◽  
Qiao Li ◽  
Kun Peng ◽  
Xian Zhang

Abstract The demodulation circuit designed in this paper is suitable for the analog front end of passive UHF RFID tag chip, which can handle ASK signals with large changes in amplitude, modulation depth and signal frequency. Its performance meets the requirements of standards ISO/IEC 18000-6C and GB/T 29768-2013. Envelope detection circuit and limiter circuit are simple in structure and do not consume power. The comparison reference voltage is taken according to the average value of the envelope high and low levels, and is less affected by the dynamic changes of the input signal. Changing the width-to-length ratio of the MOSFETs in the feedback path of the comparator can adjust the hysteresis, with strong noise suppression and controllable sensitivity. The demodulator is implemented with TSMC 0.18 μm standard CMOS process. The simulation results show that the ASK signal modulation depth that the demodulator can handle is as low as 30%, and the maximum pulse width demodulation error is only 0.43%.


2015 ◽  
Vol 6 (4) ◽  
pp. 171-184
Author(s):  
Liangbo Xie ◽  
Jiaxin Liu ◽  
Yao Wang ◽  
Chuan Yin ◽  
Guangjun Wen

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