FPGA implementation of universal random number generator

2005 ◽  
Author(s):  
Wei Cui ◽  
Chengshu Li ◽  
Xin Sun
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Number Generator

Hyperjerk multiscroll oscillators with megastability: Analysis, FPGA implementation and a novel ANN-ring-based True Random Number Generator

2019 ◽  
Vol 112 ◽  
pp. 152941 ◽  
Author(s):  
Murat Tuna ◽  
Anitha Karthikeyan ◽  
Karthikeyan Rajagopal ◽  
Murat Alcin ◽  
İsmail Koyuncu
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Number Generator ◽  
True Random Number Generator

scholarly journals FPGA Implementation of High Quality Random Number Generator Using LUT Based Shift Registers

2016 ◽  
Vol 24 ◽  
pp. 1155-1162 ◽  
Author(s):  
Remya Justin ◽  
Binu K. Mathew ◽  
Susan Abe
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Number Generator ◽  
High Quality

scholarly journals Efficient design of chaos based 4 bit true random number generator on FPGA

2018 ◽  
Vol 7 (3) ◽  
pp. 1783
Author(s):  
Ramji Gupta ◽  
Alpana Pandey ◽  
R. K.Baghel
Keyword(s):  
Secure Communication ◽  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Experimental Result ◽  
Chaotic Oscillator ◽  
Number Generator ◽  
Efficient Design ◽  
True Random Number Generator

True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite. 

scholarly journals FPGA Implementation of Metastability-Based True Random Number Generator

2012 ◽  
Vol E95.D (2) ◽  
pp. 426-436 ◽  
Author(s):  
Hisashi HATA ◽  
Shuichi ICHIKAWA
Keyword(s):  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Number Generator ◽  
True Random Number Generator

Efficient FPGA implementation of high-speed true random number generator

2021 ◽  
Vol 92 (2) ◽  
pp. 024706
Author(s):  
Zhenguo Lu ◽  
Shenshen Yang ◽  
Jianqiang Liu ◽  
Xuyang Wang ◽  
Yongmin Li
Keyword(s):  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Fpga Implementation ◽  
Number Generator ◽  
True Random Number Generator
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