Performance Evaluation of R-PLL for Robust Sensorless Operation of DFIG under Harmonics, DC Offset and Phase Jump in Grid Voltage

2021 ◽  
Author(s):  
MA Asha Rani ◽  
M Chakkarapani ◽  
C Nagamani ◽  
G Saravana Ilango ◽  
M. Jaya Bharata Reddy
Keyword(s):  
Performance Evaluation ◽  
Phase Jump ◽  
Grid Voltage ◽  
Dc Offset

scholarly journals Performance Evaluation of Three-Phase Grid-tied SPV-DSTATCOM with DC-offset Compensation Under Dynamic Load Condition

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Arobinda Dash ◽  
Durgesh Prasad Bagarty ◽  
Utkal Ranjan Muduli ◽  
Ranjan Kumar Behera ◽  
Khalifa Al Hosani ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Dynamic Load ◽  
Load Condition ◽  
Dc Offset ◽  
Three Phase ◽  
Offset Compensation

scholarly journals Benchmarking of phase lock loop based synchronization algorithms for grid-tied inverter

2019 ◽  
Vol 16 (1) ◽  
pp. 1-19 ◽  
Author(s):  
Filip Filipovic ◽  
Bojan Bankovic ◽  
Milutin Petronijevic ◽  
Nebojsa Mitrovic ◽  
Vojkan Kostic
Keyword(s):  
Reference Frame ◽  
Frequency Estimation ◽  
Wide Spectrum ◽  
Phase Lock Loop ◽  
Grid Voltage ◽  
Dc Offset ◽  
Grid Synchronization ◽  
Synchronous Reference Frame ◽  
Stationary Reference Frame ◽  
Voltage Phase

In renewable energy-based generation sources a phase locked loop is one of the most popular synchronization techniques. A rapid and precise grid voltage phase and frequency estimation under a wide spectrum of possible grid disturbances is its main objective. This paper compares popular grid synchronization algorithms on grid voltage anomalies. The compared algorithms are divided in three groups: without filtering, with filtering in synchronous reference frame and with filtering in stationary reference frame. The behaviour of the algorithms is tested in a laboratory, using dSpace 1103 as a platform on which the algorithms are compiled and OMICRON CMC 356 as a programmable grid voltage generator. The benchmarks conducted in this paper include voltage sags, grid voltages harmonics, DC offset and frequency step change. The obtained results show that there are significant differences in tested PLL responses for some networks disturbances.

scholarly journals An Adaptive Frequency Phase-Locked Loop Based on a Third Order Generalized Integrator

Energies ◽  
2019 ◽  
Vol 12 (2) ◽  
pp. 309 ◽  
Author(s):  
Heng Du ◽  
Qiuye Sun ◽  
Qifu Cheng ◽  
Dazhong Ma ◽  
Xu Wang
Keyword(s):  
Single Phase ◽  
Power Grid ◽  
Phase Locked Loop ◽  
Frequency Change ◽  
Third Order ◽  
Vector Method ◽  
Grid Voltage ◽  
Dc Offset ◽  
Voltage Frequency ◽  
Frequency Changes

In this paper, the basic principle and characteristics of a phase-locked loop (PLL) in a single phase grid-connected system are analyzed, and this paper introduces one type virtual orthogonal voltage vector method based on a third order generalized integrator (TOGI) to construct an alpha and beta static coordinate system. The TOGI structure can eliminate the DC offset in a voltage signal or zero offset in the sampling process, and ensure the amplitude of the virtual orthogonal signal is consistent. At the same time, the adaptive frequency estimation unit is introduced, which can effectively deal with the power grid voltage frequency changes and ensure the accuracy of PLL. MATLAB (R2012a, MathWorks, Natick, MA, USA) is used to simulate the variation of power grid voltage frequency, DC component injection, harmonics injection and other parameters, and the performance of PLL is adequately verified. In addition, a 5kW single-phase energy router experimental platform is built to verify the proposed PLL. The experimental results show that the PLL can well track the frequency change of the grid voltage and eliminate the DC offset, so as to achieve accurate phase tracking.

scholarly journals An Effective Solution to Eliminate DC-Offset for Extracting the Phase and Frequency of Grid Voltage

2021 ◽  
Vol 2021 ◽  
pp. 1-9
Author(s):  
Fehmi Sevilmiş ◽  
Hulusi Karaca
Keyword(s):  
Dynamic Performance ◽  
Phase Locked Loop ◽  
Experimental Results ◽  
Effective Solution ◽  
Control Loop ◽  
Slow Dynamic ◽  
Grid Voltage ◽  
Dc Offset

Recently, several approaches with the ability to reject the DC-offset in phase locked loop (PLL) methods have been developed. These approaches include different filtering structures which can be classified into two categories: prefiltering before the PLL input and in-loop filtering in the PLL control loop. As highlighted in the literature, the DC-offset rejection methods based on in-loop filtering have received less attention due to their slow dynamic performance. Therefore, this paper proposes an alternative DC-offset rejection technique as in-loop filtering of the PLL. The effectiveness of the proposed PLL is confirmed by simulation and experimental results.

scholarly journals Improved single-phase PLL structure with DC-SOGI block on FPGA board implementation

2017 ◽  
Vol 1 (1) ◽  
Author(s):  
Milica Ristović Krstić ◽  
Slobodan Lubura ◽  
Tatjana Nikolić
Keyword(s):  
High Performance ◽  
Parameters Estimation ◽  
Zero Crossing ◽  
Grid Voltage ◽  
Dc Offset ◽  
Grid Synchronization ◽  
Pv Inverter ◽  
Long Time ◽  
Sine Signal ◽  
The One

Synchronization block which is used as a part of photovoltaic (PV) inverters control structure has a key impact on connectinginverters with grid. One of the most important parameters in the point of connection PV inverter and grid is phase angle between gridvoltage and inverter current. This angle determines the energy transfer between inverter and grid. Synchronization algorithms havedeveloped for very long time. At first, they were based on zero crossing grid voltage detection, while today complexed synchronizationalgorithms implemented on high performance digital board have been used. One of these synchronization structures is Phase LockedLoop – PLL. In this paper implementation of improved PLL structure is presented. This improved structure is special while it haspossibility of grid parameters estimation even if grid voltage has noise or DC offset. This DC offset from the grid in PLL structureusually entered via measurement and A/D conversion processor or may be generated due to temporary system faults. Appearance ofDC offset in measured grid voltage on the one hand prevents any estimation process of grid parameters and on the other hand alsodegrades reference sine signal at the output of PLL structure in PV inverters. This improved structure is designed in digital form andimplemented on FPGA digital board and experimental results of this implementation are presented. Obtained experimental resultsshow that the proposed PLL structure successfully solves important issue such is presence of DC offset in measured grid voltage.

scholarly journals Design of an advanced PLL for accurate phase angle extraction under grid voltage HIHs and DC offset

2018 ◽  
Vol 11 (6) ◽  
pp. 995-1008 ◽  
Author(s):  
Zunaib Ali ◽  
Nicholas Christofides ◽  
Lenos Hadjidemetriou ◽  
Elias Kyriakides
Keyword(s):  
Phase Angle ◽  
Grid Voltage ◽  
Dc Offset

scholarly journals DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

2022 ◽  
Vol 7 (1) ◽  
Author(s):  
Issam A. Smadi ◽  
Bayan H. Bany Fawaz
Keyword(s):  
Single Phase ◽  
Dynamic Performance ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Second Order ◽  
Frequency Variation ◽  
Grid Voltage ◽  
Dc Offset ◽  
Grid Synchronization ◽  
Grid Connected Converters

AbstractFast and accurate monitoring of the phase, amplitude, and frequency of the grid voltage is essential for single-phase grid-connected converters. The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters. In this paper, a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation (ADSC) in a second-order generalized integrator (SOGI) phase-locked loop (PLL). A frequency-fixed SOGI-based PLL (FFSOGI-PLL) is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs. A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral (PI) controller gains. The effects of frequency variation and ADSC on the proposed PLL are considered, and correction methods are adopted to accurately estimate grid information. The simulation results are presented, along with comparisons to other single-phase PLLs in terms of settling time, peak frequency, and phase error to validate the proposed PLL. The dynamic performance of the proposed PLL is also experimentally validated. Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices, offering an improved solution for precise grid synchronization in single-phase applications.

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