Compartmentalized Covariance Intersection: A Novel Filter Architecture for Distributed Localization*

Author(s):  
Adam Wiktor ◽  
Stephen Rock
2019 ◽  
Vol 118 (7) ◽  
pp. 73-76
Author(s):  
Sharanabasappa ◽  
P Ravibabu

Nowadays, during the process of Image acquisition and transmission, image information data can be corrupted by impulse noise. That noise is classified as salt and pepper noise and random impulse noise depending on the noise values. A median filter is widely used digital nonlinear filter  in edge preservation, removing of impulse noise and smoothing of signals. Median filter is the widely used to remove salt and pepper noise than rank order filter, morphological filter, and unsharp masking filter. The median filter replaces a sample with the middle value among all the samples present inside the sample window. A median filter will be of two types depending on the number of samples processed at the same cycle i.e, bit level architecture and word level architecture.. In this paper, Carry Look-ahead Adder median filter method will be introduced to improve the hardware resources used in median filter architecture for 5 window and 9 window for 8 bit and 16 bit median filter architecture.


1994 ◽  
pp. 159-172
Author(s):  
Naresh R. Shanbhag ◽  
Keshab K. Parhi

2002 ◽  
Vol 15 (3) ◽  
pp. 451-464 ◽  
Author(s):  
Ivan Milentijevic ◽  
Vladimir Ciric ◽  
Teufik Tokic ◽  
Oliver Vojinovic

The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor on to the fixed size array is described in this paper. The bit-level transformation of the original data flow graph (DFG), for the bit-plane architecture, that provides the successful application of the folding technique with changeable folding is presented at transfer function level The mathematical path that describes the transformation is given, and implications at the DFG level are discussed. Changeable folding sets are involved with aim to increase the throughput of the folded system reducing the folding factor according to the coefficient length. The folded FIR filter architecture is described in VHDL as a parameterized FIR filtering core and implemented in FPGA technology. The design "tradeoffs" relating on the occupation of the chip resources and achieved throughputs are presented.


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