FPGA design and implementation of the Joint Viterbi Detector Decoder

Author(s):  
Brahim Hamadicharef ◽  
Kheong Sann Chan
2013 ◽  
Vol 427-429 ◽  
pp. 806-809 ◽  
Author(s):  
Lei Wang ◽  
Yan Yan Yu ◽  
Qian Huang ◽  
Jun Yang ◽  
Zheng Peng Zhao

This paper introduces the principle of digital signature algorithm MD5, focused on the calculation phase of the algorithm, the algorithm structure iteration of the loop, and to optimize its calculation phase, and given FPGA design icon, the experiment can be drawn based on FPGA with less resource, fast implementation of the MD5 algorithm. The hardware implementation of the MD5 hash algorithm HMACs build encryption accelerator which has some practical value.


Author(s):  
Jorge Martinez-Carballido ◽  
Jorge Guevara-Escobedo ◽  
Juan M. Ramirez-Cortes ◽  
Ruben Alejos-Palomares

Sign in / Sign up

Export Citation Format

Share Document