FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2004.838266 ◽

2005 ◽

Vol 52 (2) ◽

pp. 350-365 ◽

Author(s):

Man Guo ◽

M.O. Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Fpga Design ◽

Design And Implementation

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FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM

Wireless Engineering and Technology ◽

10.4236/wet.2012.33019 ◽

2012 ◽

Vol 03 (03) ◽

pp. 125-131 ◽

Author(s):

Yan Sun ◽

Zhizhong Ding

Keyword(s):

Viterbi Decoder ◽

Fpga Design ◽

Design And Implementation ◽

Convolutional Encoder

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A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1205960 ◽

2003 ◽

Author(s):

Man Guo ◽

M. Omair Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Fpga Implementation ◽

Viterbi Decoder

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Low power state-parallel relaxed adaptive Viterbi decoder design and implementation

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693707 ◽

2006 ◽

Author(s):

Fei Sun ◽

Tong Zhang

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Design And Implementation ◽

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FPGA Design and Implementation of Low Power Consumption LDPC Encoder Based on DVB-S2

Lecture Notes in Electrical Engineering - Advances in Computer, Communication, Control and Automation ◽

10.1007/978-3-642-25541-0_12 ◽

2011 ◽

pp. 85-92

Author(s):

Xingyu Zou ◽

Hui Qian ◽

Shuying Cheng

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Fpga Design ◽

Design And Implementation

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Low-Power Systolic Array Viterbi Decoder Implementation With A Clock-gating Method

The KIPS Transactions PartA ◽

10.3745/kipsta.2005.12a.1.001 ◽

2005 ◽

Vol 12A (1) ◽

pp. 1-6

Author(s):

Je-Hyuk Ryu ◽

Jun-Dong Cho

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Clock Gating ◽

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Low power, dynamically reconfigurable, memoryless systolic array based architecture for Viterbi decoder

2011 International Conference on Energy, Automation and Signal ◽

10.1109/iceas.2011.6147135 ◽

2011 ◽

Author(s):

A. K. Mishra ◽

P. P. Jiju

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Dynamically Reconfigurable

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Design and Implementation of Low Power High Speed Viterbi Decoder

Procedia Engineering ◽

10.1016/j.proeng.2012.01.834 ◽

2012 ◽

Vol 30 ◽

pp. 61-68 ◽

Author(s):

K. Cholan

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Design And Implementation

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Ultra - Low - Power Asynchronous Processor and FPGA Design using Straintronics Nanomagnets

10.21236/ada584514 ◽

2013 ◽

Author(s):

Pinaki Maumder

Keyword(s):

Low Power ◽

Fpga Design ◽

Ultra Low Power

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Design and Implementation of a Low Power Ternary Content Addressable Memory (TCAM)

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9333092 ◽

2020 ◽

Author(s):

Karthik S ◽

Karthick D ◽

Sanjaya M V ◽

Madhav Rao

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Design And Implementation ◽

Ternary Content Addressable Memory

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Low power FPGA design using hybrid CMOS-NEMS approach

Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 ◽

10.1145/1283780.1283785 ◽

2007 ◽

Author(s):

Yu Zhou ◽

Shijo Thekkel ◽

Swarup Bhunia

Keyword(s):

Low Power ◽

Fpga Design ◽

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