A Ternary Memristive Logic-in-Memory Design for Fast Data Scan

Mapping Intimacies ◽

10.1109/icta53157.2021.9661630 ◽

2021 ◽

Author(s):

Tianhong Shen ◽

Yanan Sun ◽

Weifeng He ◽

Zhi Li ◽

Weiyi Liu ◽

...

Keyword(s):

Download Full-text

Thread Batching for High-performance Energy-efficient GPU Memory Design

ACM Journal on Emerging Technologies in Computing Systems ◽

10.1145/3330152 ◽

2019 ◽

Vol 15 (4) ◽

pp. 1-21

Author(s):

Bing Li ◽

Mengjie Mao ◽

Xiaoxiao Liu ◽

Tao Liu ◽

Zihao Liu ◽

...

Keyword(s):

Energy Efficient ◽

High Performance ◽

Download Full-text

Compact Single-Phase-Search Multistate Content-Addressable Memory Design Using One FeFET/Cell

IEEE Transactions on Electron Devices ◽

10.1109/ted.2020.3039477 ◽

2020 ◽

pp. 1-9

Author(s):

Ramin Rajaei ◽

Mohammad Mehdi Sharifi ◽

Arman Kazemi ◽

Michael Niemier ◽

Xiaobo Sharon Hu

Keyword(s):

Single Phase ◽

Content Addressable Memory ◽

Download Full-text

16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

2021 IEEE International Solid- State Circuits Conference (ISSCC) ◽

10.1109/isscc42613.2021.9365932 ◽

2021 ◽

Author(s):

Shanshan Xie ◽

Can Ni ◽

Aseem Sayal ◽

Pulkit Jain ◽

Fatih Hamzaoglu ◽

...

Keyword(s):

Data Converters ◽

Dynamic Memory ◽

Memory Design ◽

Download Full-text

An N-Channel Band-to-Band Tunneling Flash Memory Design Optimization

Solid State Electronics Letters ◽

10.1016/j.ssel.2021.02.001 ◽

2020 ◽

Vol 2 ◽

pp. 140-145

Author(s):

Wing-Kong Ng ◽

Wing-Shan Tam ◽

Chi-Wah Kok

Keyword(s):

Design Optimization ◽

Flash Memory ◽

Memory Design ◽

Band To Band Tunneling

Download Full-text

A soft error robust and power aware memory design

Proceedings of the 20th annual conference on Integrated circuits and systems design - SBCCI '07 ◽

10.1145/1284480.1284560 ◽

2007 ◽

Author(s):

Costas Argyrides ◽

Carlos A. Lisboa ◽

Luigi Carro ◽

Dhiraj K. Pradhan

Keyword(s):

Download Full-text

Memory design for micros

Microelectronics Reliability ◽

10.1016/0026-2714(79)90590-0 ◽

1979 ◽

Vol 19 (5-6) ◽

pp. 453-455

Author(s):

Dave Lewis

Keyword(s):

Download Full-text

Selectively multiple-valued memory design using negative differential resistance circuits implemented by standard SiGe BiCMOS process

2008 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2008.4657954 ◽

2008 ◽

Author(s):

Dong-Shong Liang ◽

Cheng-Chi Tai ◽

Kwang-Jow Gan ◽

Yi-Zhi Lin

Keyword(s):

Negative Differential Resistance ◽

Differential Resistance ◽

Memory Design ◽

Sige Bicmos ◽

Download Full-text

16-k RAM eases memory design for mainframes and microcomputers

Microelectronics Reliability ◽

10.1016/0026-2714(77)90245-1 ◽

1977 ◽

Vol 16 (5) ◽

pp. 555

Keyword(s):

Download Full-text

Frame memory design in a flicker-free field-sequential stereoscopic TV system

10.1117/12.311092 ◽

1998 ◽

Author(s):

Hongbo Sun

Keyword(s):

Download Full-text

Preferential Memory Design for MBC Frameworks

Computing with Memory for Energy-Efficient Robust Systems ◽

10.1007/978-1-4614-7798-3_13 ◽

2013 ◽

pp. 125-136

Author(s):

Somnath Paul ◽

Swarup Bhunia

Keyword(s):

Download Full-text