A 1st-order noise shaping SAR ADC with dual-capacitor merge-and-split switching scheme for sensor chip

Mapping Intimacies ◽

10.1109/icta53157.2021.9661932 ◽

2021 ◽

Author(s):

Xin Xin ◽

Shimei Zhao ◽

Yuanhao Hu ◽

Xingyuan Tong

Keyword(s):

Sar Adc ◽

Sensor Chip ◽

Noise Shaping ◽

Switching Scheme

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An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993655 ◽

2017 ◽

Author(s):

Masaya Miyahara ◽

Akira Matsuzawa

Keyword(s):

Dynamic Range ◽

Open Loop ◽

Sar Adc ◽

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A 1st-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401115 ◽

2021 ◽

Author(s):

Hanrui Zhang ◽

Nannan Li ◽

Zihao Jiao ◽

Jie Zhang ◽

Xiaofei Wang ◽

...

Keyword(s):

Sar Adc ◽

Noise Shaping ◽

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OTA-Free MASH 2–2 Noise Shaping SAR ADC: System and Design Considerations

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180832 ◽

2020 ◽

Author(s):

Masoume Akbari ◽

Mohammad Honarparvar ◽

Yvon Savaria ◽

Mohamad Sawan

Keyword(s):

Sar Adc ◽

Noise Shaping ◽

Design Considerations

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A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC

2019 IEEE 13th International Conference on ASIC (ASICON) ◽

10.1109/asicon47005.2019.8983604 ◽

2019 ◽

Author(s):

Longheng Luo ◽

Xingchen Shen ◽

Jianguo Diao ◽

Fan Ye ◽

Junyan Ren

Keyword(s):

Sar Adc ◽

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A 960μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme

Microelectronics Journal ◽

10.1016/j.mejo.2013.08.012 ◽

2013 ◽

Vol 44 (12) ◽

pp. 1260-1267 ◽

Author(s):

Yue Wu ◽

Xu Cheng ◽

Xiaoyang Zeng

Keyword(s):

Energy Efficient ◽

Sar Adc ◽

Switching Scheme ◽

Capacitor Switching

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An energy-efficient switching scheme based on the improved semi-resting DAC structure and floating-capacitor technique for SAR ADC

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-021-01910-2 ◽

2021 ◽

Author(s):

Yi Huang ◽

Linlin Huang ◽

Jianhui Wu

Keyword(s):

Energy Efficient ◽

Sar Adc ◽

Switching Scheme ◽

Floating Capacitor

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Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique

JSTS Journal of Semiconductor Technology and Science ◽

10.5573/jsts.2021.21.5.297 ◽

2021 ◽

Vol 21 (5) ◽

pp. 297-303

Author(s):

Ki-Hyun Kim ◽

Ji-Hyun Baek ◽

Jong-Hyun Kim ◽

Hyung-Il Chae

Keyword(s):

Error Correction ◽

Sar Adc ◽

Noise Shaping ◽

Correction Technique ◽

Time Interleaved

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A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008491 ◽

2017 ◽

Author(s):

Ying-Zu Lin ◽

Chih-Hou Tsai ◽

Shan-Chih Tsou ◽

Rong-Xing Chu ◽

Chao-Hsin Lu

Keyword(s):

Sar Adc ◽

Noise Shaping ◽

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A highly energy-efficient, highly area-efficient capacitance multiplexing switching scheme for SAR ADC

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-018-1217-2 ◽

2018 ◽

Vol 96 (1) ◽

pp. 207-215 ◽

Author(s):

Jian Liu ◽

Ruixue Ding ◽

Shubin Liu ◽

Zhangming Zhu

Keyword(s):

Energy Efficient ◽

Sar Adc ◽

Switching Scheme ◽

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A 2.1 mW 2 MHz-BW 73.8 dB-SNDR Buffer-Embedded Noise-Shaping SAR ADC

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2021.3109991 ◽

2021 ◽

pp. 1-9

Author(s):

Taewoong Kim ◽

Youngcheol Chae

Keyword(s):

Sar Adc ◽

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