2017 Symposium on VLSI Circuits
Latest Publications

TOTAL DOCUMENTS

144

(FIVE YEARS 0)

H-INDEX

11

(FIVE YEARS 0)

Published By IEEE

9784863486140

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008491 ◽

2017 ◽

Author(s):

Ying-Zu Lin ◽

Chih-Hou Tsai ◽

Shan-Chih Tsou ◽

Rong-Xing Chu ◽

Chao-Hsin Lu

Keyword(s):

Sar Adc ◽

Noise Shaping ◽

Download Full-text

A hybrid power amplifier using 3-phase 3-level class-D with 200nH inductors and current balancing technique

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008460 ◽

2017 ◽

Author(s):

Jun-Han Choi ◽

Gyu-Hyeong Cho

Keyword(s):

Power Amplifier ◽

Phase 3 ◽

Hybrid Power ◽

Download Full-text

A 31.2pJ/disparity· pixel stereo matching processor with stereo SRAM for mobile UI application

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008464 ◽

2017 ◽

Author(s):

Jinsu Lee ◽

Dongjoo Shin ◽

Kyuho Lee ◽

Hoi-Jun Yoo

Keyword(s):

Stereo Matching

Download Full-text

A 107 dB SFDR, 80 kS/s Nyquist-rate SAR ADC using a hybrid capacitive and incremental ΣΔ DAC

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008494 ◽

2017 ◽

Author(s):

Ahmad AlMarashli ◽

Jens Anders ◽

Joachim Becker ◽

Maurits Ortmanns

Keyword(s):

Sar Adc ◽

Download Full-text

A 65nm CMOS I/Q RF power DAC with 24–42dB 3rd harmonic cancellation and up to 18dB mixed-signal filtering

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008517 ◽

2017 ◽

Author(s):

Bonjern Yang ◽

Eric Y. Chang ◽

Ali Niknejad ◽

Borivoje Nikolic ◽

Elad Alon

Keyword(s):

Rf Power ◽

Signal Filtering ◽

Mixed Signal ◽

Harmonic Cancellation

Download Full-text

A true two-quadrant fully integrated switched capacitor DC-DC converter supporting vertically stacked DVS-loads with up to 99.6% efficiency

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008486 ◽

2017 ◽

Author(s):

Athanasios Sarafianos ◽

Michiel Steyaert

Keyword(s):

Switched Capacitor ◽

Fully Integrated

Download Full-text

3.37 μW/Ch modular scalable neural recording system with embedded lossless compression for dynamic power reduction

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008468 ◽

2017 ◽

Author(s):

Sung-Yun Park ◽

Jihyun Cho ◽

Euisik Yoon

Keyword(s):

Lossless Compression ◽

Neural Recording ◽

Power Reduction ◽

Recording System ◽

Dynamic Power ◽

Neural Recording System

Download Full-text

Performance boost of crystalline In-Ga-Zn-O material and transistor with extremely low leakage for IoT normally-off CPU application

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008580 ◽

2017 ◽

Author(s):

Shao Hui Wu ◽

X Y Jia ◽

Xiang Li ◽

Chi Chang Shuai ◽

Hung Chan Lin ◽

...

Keyword(s):

Download Full-text

An 8GHz, 0.005mm2 all digital clock generator having 0.1% frequency accuracy by new ZTC algorithm

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008456 ◽

2017 ◽

Author(s):

Wooseok Kim ◽

Taeik Kim ◽

Jihyun Kim ◽

Hyungjong Ko

Keyword(s):

Clock Generator ◽

Download Full-text

A distance-immune low-power 4-Mbps inductively-coupled bidirectional data link

2017 Symposium on VLSI Circuits ◽

10.23919/vlsic.2017.8008548 ◽

2017 ◽

Author(s):

Alireza Yousefi ◽

Dihang Yang ◽

Asad A. Abidi ◽

Dejan Markovic

Keyword(s):

Low Power ◽

Data Link ◽

Inductively Coupled

Download Full-text