Optimization-Based Capacitor Balancing Method with Selective DC Current Ripple Reduction for CHB Converters

From its introduction to the present day, Cascaded H-Bridge multilevel converters were employed on numerous applications. However, their floating capacitor, while advantageous for some applications (such as photovoltaic) requires the usage of balancing methods by design. Over the years, several such methods were proposed and polished. Some of these methods use optimization techniques or inject a zero-sequence voltage to take advantage of the converter redundancies. This paper describes an optimization-based capacitor balancing method with additional features. It can drive each module DC-Link to a different voltage for independent maximum power point tracking in photovoltaic applications. Moreover, the user can specify the independent active power set points to modules connected to batteries or any other energy storage systems. Finally, DC current ripple can be reduced on some modules, which can extend the lifespan of any connected ultra-capacitors. The method as a whole is tested on real hardware and compared with the state-of-the-art. In its simplest configuration, the presented method shows greater speed, robustness, and current wave quality than the state-of-the-art alternative in spite of producing about 1/3 fewer commutations. Its other characteristics provide additional functionalities and improve the adaptability of the converter to other applications.

A new seven level boost-type ANPC inverter topology for photovoltaic applications

Developing of new photovoltaic inverter topologies is received more attention in the last few years. In particular, designing an active neutral-point-clamping inverter type structure is quite popular for PV applications. The output voltage is always half of the input voltage (vin), which further increases the voltage rating of dc-link capacitors in the conventional three-level ANPC. To rectify the above problem and increase the output voltage by reducing dc-link capacitors voltage rating, a new boost type seven-level ANPC inverter topology is proposed. The proposed topology consists of seven switches and one floating capacitor. The floating capacitor voltage is self-balanced, and the output voltage is 1.5 times higher than the input voltage. A detailed comparison for some power components, power loss and cost with other existing topologies are presented. Further, the proposed topology is validated in a prototype hardware setup for different load values.

Electronically Tunable First Order AP/LP and LP/HP Filter Topologies Using Electronically Controllable Second Generation Voltage Conveyor (CVCII)

In this paper two new first order filter topologies realizing low-pass/all-pass (LP/AP) and low-pass/high-pass (LP/HP) outputs using electronically controllable second generation voltage conveyors (CVCIIs) are presented. Unlike second generation voltage conveyors (VCII), in CVCII each performance parameter, including ports, parasitic impedances, current and/or voltage gains can be electronically varied. Here, in particular, the proposed filter topologies are based on two CVCIIs, one resistor and one capacitor. In the first topology VLP/IAP/VAP and in the second topology ILP/VLP/IHP/VHP outputs are achievable, respectively. However, the current and voltage outputs are not achievable simultaneously and a floating capacitor is used. A control current (Icon) is used to change the first CVCII Y port impedance, which sets the filter −3 dB frequency (F0) of all the outputs. Moreover, in the second topology, the gains of HP and AP outputs are electronically adjusted by means of a control voltage (Vcon). Favorably, no restricting matching condition is necessary. PSpice simulations using 0.18 µm CMOS technology and supply voltages of ±0.9V show that by changing Icon from 0.5 µA to 50 µA, F0 is varied from 89 kHz to 1 MHz. Similarly, for a Vcon variation from −0.9 V to 0.185 V, the gains of IAP and IHP vary from 30 dB to 0 dB and those of VAP and VHP vary from 100 dB to 20 dB. The total harmonic distortion (THD) is about 8%. The power consumption is from 0.385 mW to 1.057 mW.