Wavelet Compression of Multichannel ECG Data by Enhanced Set Partitioning in Hierarchical Trees Algorithm

Author(s):  
Ershad Sharifahmadian

Wavelet based image compression standards not only inspired signal and image processing community but also the research community of many research and application fields towards the wavelet theory. All wavelet based schemes follow the standard sequence of steps. They are transformation and the processing task at one end followed by the inverse of processing task and inverse transform at another end. Wavelet based compression was done in a quite different manner from its inception. The early techniques include Embedded Zerotree Wavelet (EZW) coding and Set Partitioning in Hierarchical Trees (SPIHT) coding. Although, SPIHT is an extension of EZW, both follow more or less similar process in coding and decoding. These schemes code the significant and insignificant coefficients using symbols or maintaining a list of indices of the coefficients. The decision on significant or insignificant will be taken by comparing with a threshold which will be updated in each iteration. In both the schemes, if a coefficient is identified as an insignificant one, then the bits incurred in conveying this coefficient is less and in many cases very less. One can imagine that if a coefficient is made to be an insignificant then the number of bits required will be less. This issue was taken up in this paper and bits of selected regions is chosen and a significant improvement is compression ratio is observed at a little cost of quality.


2013 ◽  
Vol 2013 ◽  
pp. 1-26 ◽  
Author(s):  
Jia Hao Kong ◽  
Li-Minn Ang ◽  
Kah Phooi Seng

The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor’s application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system.


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