Parallel field programmable gate array particle filtering architecture for real-time neural signal processing

Author(s):  
J Mountney ◽  
D Silage ◽  
I Obeid
2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.


2009 ◽  
Vol 36 (2) ◽  
pp. 307-311
Author(s):  
罗凤武 Luo Fengwu ◽  
王利颖 Wang Liying ◽  
涂霞 Tu Xia ◽  
陈厚来 Chen Houlai

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