A Low-Complexity Layered Decoding Algorithm for LDPC Codes

2009 ◽  
Author(s):  
Wang Zhongxun ◽  
Mu Qing
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
Decoding Algorithm ◽  
Layered Decoding

scholarly journals A Parallel Layered Decoding Algorithm for Non-layered LDPC Codes

2010 ◽  
Vol 32 (8) ◽  
pp. 1956-1960
Author(s):  
Kun Guo ◽  
Yong Hei ◽  
Yu-mei Zhou ◽  
Shu-shan Qiao
Keyword(s):  
Ldpc Codes ◽  
Decoding Algorithm ◽  
Layered Decoding

A BP Decoding Algorithm Based on Nodes Residual for LDPC Codes and its Hardware Implementation

2011 ◽  
Vol 128-129 ◽  
pp. 7-10
Author(s):  
Zhong Xun Wang ◽  
Xing Cheng Wang ◽  
Fang Qiang Zhu
Keyword(s):  
Hardware Implementation ◽  
Belief Propagation ◽  
Dynamic Scheduling ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Decoding Algorithm ◽  
Fast Decoding ◽  
Good For

We researched BP decoding algorithm based on variable-to-check information residual for LDPC code (VC-RBP) in this paper. It is a dynamic scheduling belief propagation using residuals, and has some advantages，such as fast decoding, good performance, and low complexity. It is similar to residual belief propagation (RBP),but has some difference in computing the residual message. This paper further optimized the new algorithm on DSP of TMS320dm6446, and it is good for hardware implementation.

scholarly journals Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm

2018 ◽  
Vol 7 (03) ◽  
pp. 23781-23784
Author(s):  
Rajarshini Mishra
Keyword(s):  
Variance Estimation ◽  
Cyclic Codes ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Xilinx Fpga

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

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