FPGA Implementation of Low-Latency Robust Asynchronous Interfaces for GALS Systems

2018 ◽  
Author(s):  
Tiago Curtinhas ◽  
Duarte L. Oliveira ◽  
Osamu Saotome ◽  
Joao B. Brandolin
Keyword(s):  
Fpga Implementation ◽  
Low Latency ◽  
Gals Systems

scholarly journals FPGA Implementation of Hardware Architecture for H264/AV Codec Standards

2013 ◽  
Vol 2 (01) ◽  
pp. 01-07
Author(s):  
Prof. Naveen Jain
Keyword(s):  
Wireless Networks ◽  
Discrete Cosine Transform ◽  
Video Compression ◽  
High Throughput ◽  
Low Complexity ◽  
Prediction Equation ◽  
Parallel Process ◽  
Fpga Implementation ◽  
Low Latency ◽  
Efficient Utilization

The proposed work is a modern hardware based architecture for performing transformation, quantisation and prediction is designed which is used for H.264/AVC video standards. This designed hardware find its importance in advanced H264 encoders which are repeatedly find its application in HDTV applications. The H264/AV Codec does video compression and video decompression for prospect broadband and wireless networks.  A low complexity discrete cosine transform is used by DSP embedded multiplier. An intra-prediction equation are employed to get low latency, high throughput, efficient utilization of resources. The proposed architecture also employs both pipeline & parallel process methods. The proposed architecture is implemented using VHDL and synthesised for Virtex 5, and the device is 5vlx50tff665.

scholarly journals FPGA Implementation of Radix-2 based FFT Architecture for Real-Valued signal processing

2019 ◽  
Vol 8 (6) ◽  
pp. 596-601
Keyword(s):  
Signal Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
High Throughput ◽  
Fpga Implementation ◽  
Low Latency ◽  
New Approach ◽  
Hardware Resource ◽  
Reversed Order

This paper investigates the various pipelined FFT architectures based on radix-2, radix-2 2 & radix-2 3 algorithms. The implemented FFTs are designed by employing techniques such as folded transform and register minimization. It maximizes the utilization of hardware resource and reduces the number of adders. It requires less area and achieves high throughput and low latency. For higher values of N, the FFT (Fast Fourier Transform) architecture has many butterfly structures which has been optimized. The FFT outputs are usually obtained in a bit reversed order and a new approach for reordering the bit-reversed orders has been proposed.

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