An Area-Efficient SPHINCS+ Post-Quantum Signature Coprocessor

2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) ◽

10.1109/ipdpsw52791.2021.00034 ◽

2021 ◽

Author(s):

Quentin Berthet ◽

Andres Upegui ◽

Laurent Gantel ◽

Alexandre Duc ◽

Giulia Traverso

Keyword(s):

Quantum Signature ◽

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Design of an Area-Efficient and Low-Power Hierarchical NoC Architecture Based on Circuit Switching

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.890 ◽

2009 ◽

Vol E92-A (3) ◽

pp. 890-899

Author(s):

Woo Joo KIM ◽

Sung Hee LEE ◽

Sun Young HWANG

Keyword(s):

Low Power ◽

Circuit Switching ◽

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Post-quantum digital signature schemes: setting a hidden group with two-dimensional cyclicity

Informatization and communication ◽

10.34219/2078-8320-2020-11-4-75-82 ◽

2020 ◽

Vol 4 ◽

pp. 75-82

Author(s):

D.Yu. Guryanov ◽

◽

D.N. Moldovyan ◽

A. A. Moldovyan ◽

Keyword(s):

Associative Algebra ◽

Digital Signature ◽

Quantum Signature ◽

Commutative Group ◽

Two Dimensional ◽

Signature Scheme ◽

Signature Schemes ◽

Fixed Element ◽

Commutative Associative Algebra ◽

Quantum Digital Signature

For the construction of post-quantum digital signature schemes that satisfy the strengthened criterion of resistance to quantum attacks, an algebraic carrier is proposed that allows one to define a hidden commutative group with two-dimensional cyclicity. Formulas are obtained that describe the set of elements that are permutable with a given fixed element. A post-quantum signature scheme based on the considered finite non-commutative associative algebra is described.

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Low-Power and Area-Efficient Approximate Parallel Design Using Bypassing

SSRN Electronic Journal ◽

10.2139/ssrn.3428931 ◽

2019 ◽

Author(s):

Anushka Prakash B ◽

Noah Kiran Nandi ◽

Marimuthu R ◽

Balamurugan S ◽

Duraivel A.N.

Keyword(s):

Low Power ◽

Parallel Design ◽

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

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Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2019.8754423 ◽

2019 ◽

Author(s):

Diptesh Datta ◽

Piyush Dewangan ◽

Neelam Surana ◽

Joycee Mekie

Keyword(s):

Content Addressable Memory ◽

Ternary Content Addressable Memory ◽

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Area Efficient Approximate 4–2 Compressor for Multiplier Design

2020 IEEE India Council International Subsections Conference (INDISCON) ◽

10.1109/indiscon50162.2020.00055 ◽

2020 ◽

Author(s):

Chinthalgiri Jyothi ◽

Kuruva Gayathri ◽

Saranya Karunamurthi ◽

Sreehari Veeramachaneni ◽

Noor Mahammad S

Keyword(s):

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Comparison Of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401768 ◽

2021 ◽

Author(s):

Ankita Ahuja ◽

Komail Badami ◽

Cedric Barbelenet ◽

Stephane Emery

Keyword(s):

Sar Adc ◽

Capacitive Dac ◽

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A Self-Powered and Area Efficient SSHI Rectifier for Piezoelectric Harvesters

IEEE Access ◽

10.1109/access.2021.3107365 ◽

2021 ◽

Vol 9 ◽

pp. 117703-117713 ◽

Author(s):

Salar Chamanian ◽

Berkay Ciftci ◽

Ali Muhtaroglu ◽

Haluk Kulah

Keyword(s):

Self Powered ◽

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Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2020.3036385 ◽

2020 ◽

pp. 1-10

Author(s):

Chenbing Qu ◽

Zhangming Zhu ◽

Yunfei En ◽

Liwei Wang ◽

Xiaoxian Liu

Keyword(s):

Rf Applications ◽

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Design of an Area Efficient Quantum Dot Cellular Automata Based Full Adder Cell Having Low Latency

2021 2nd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST) ◽

10.1109/icrest51555.2021.9331135 ◽

2021 ◽

Author(s):

Upal Barua Joy ◽

Shourov Chakraborty ◽

Sumaiya Tasnim ◽

Md Shahadat Hossain ◽

Abdul Hasib Siddique ◽

...

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Low Latency ◽

Quantum Dot Cellular Automata ◽

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