A low-power low-noise amplifier in 0.35-μm SOI CMOS technology

Author(s):  
E. Zencir ◽  
N.S. Dogan ◽  
E. Arvas ◽  
M. Ketel
2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  


2010 ◽  
Vol 57 (4) ◽  
pp. 773-782 ◽  
Author(s):  
Ali Meaamar ◽  
Chirn Chye Boon ◽  
Kiat Seng Yeo ◽  
Manh Anh Do

2008 ◽  
Vol 51 (2) ◽  
pp. 423-426 ◽  
Author(s):  
J.-X. Liu ◽  
H.-C. Kuo ◽  
Y.-K. Chu ◽  
J.-F. Yeh ◽  
H.-R. Chuang

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