scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.


2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  


2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.


Frequenz ◽  
2020 ◽  
Vol 74 (3-4) ◽  
pp. 137-144 ◽  
Author(s):  
Dheeraj Kalra ◽  
Manish Kumar ◽  
Aasheesh Shukla ◽  
Laxman Singh ◽  
Zainul Abdin Jaffery

AbstractThis paper includes a design analysis of an inductorless low-power (LP) low-noise amplifier (LNA) with active load for Ultra Wide Band (UWB) applications. The proposed LNA consists of two parallel paths, one is the common source (CS) path and second is the CG path. The CG path has the edge advantage of improving overall Noise figure (NF) due to wide band impedance matching in UWB, while the CS path provides high power gain. A method for noise cancellation is adopted, to reduce the noise of CS path with the help of CG path. The proposed LNA successfully simulated in 90 nm CMOS technology. The results of proposed work indicate optimization at frequency 5.70 GHz with 3 dB bandwidth of 4.3 GHz–8.9 GHz. All simulations have been done for a range of frequency 03 GHz–13 GHz in Cadence virtuoso software. The results quoted 1.15 dB NF, −18.12 dB S11, 13.7 dB S21, maximum operating power gain (GP) 11.756 dB at frequency 5.7 GHz and available power gain (GA) is 10.17 dB at frequency 8.61 GHz, with 0.6 V, 0.92 mW broad band LNA.


2012 ◽  
Vol 605-607 ◽  
pp. 2057-2061
Author(s):  
Xin Yin ◽  
Yi Yao ◽  
Jin Ling Jia

This paper studies a low noise amplifier design method for 5.8G wireless local area network. Using the software of designing RF circuit ADS(Advanced Design System) and Avago Technologies’s ATF-36077,we designed a three-cascade LNA. In 5.725G~5.85GHz range, noise figure less than 0.5dB, more than 30dB gain, input and output standing wave ratio less than 1.3dB.The LNA meet the design requirements.


Author(s):  
Toulali Islam ◽  
Lahbib Zenkouar

<p>Balanced amplifier is the structure proposed in this article, it provides better performance. In fact, the single amplifier meets the specification for noise figure and gain but fails to meet the return loss specification due to the large mis-matches on the input &amp; outputs. To overcome this problem one solution is to use balanced amplifier topography. In this paper, a wide-band and highgain microwave balanced amplifier constituted with branch line coupler circuit is proposed. The amplifier is unconditionally stable in the band [9-13] GHz where the gain is about 20dB. The input reflection (S11) and output return loss (S22) at 11 GHz are -33.4dB and -33.5dB respectively.</p>


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